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ADDITION

muneebullashariff edited this page Feb 12, 2024 · 1 revision

Addition example:

DESIGN

`timescale 1ns/1ns   
module adder(a,b,sum);
input wire [3:0]a,b;
output reg [3:0]sum;

assign sum=a+b;
endmodule

TESTBENCH

`timescale 1ns/1ns
`include "adder.sv"
module adder_tb;
reg [3:0]a,b;
wire [3:0]sum;

adder add(.a(a),.b(b),.sum(sum));
initial begin
$dumpfile("dump.vcd");
$dumpvars();

a=5;
b=10;

#10

a=2;
b=4;

#10

a=4;
b=3;


#10

a=6;
b=9;
$display("THIS IS A SIMPLE CODE FOR ADDING TWO NUMBERS");
#15 $finish;
end
endmodule

OUTPUT:

image

WAVEFORM

image