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project.html
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<!DOCTYPE html>
<html>
<head>
<meta charset='utf-8'>
<meta content='IE=edge' http-equiv='X-UA-Compatible'>
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<script src="https://code.iconify.design/1/1.0.7/iconify.min.js"></script>
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<title>Mehran Goli</title>
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<div class='container' id='main-container'>
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<ul class='nav nav-pills nav-stacked'>
<li role='presentation'>
<a href='index.html'>
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<div class='text'>About me</div>
</a>
</li>
<li role='presentation'>
<a href='research.html'>
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<div class='text'>Research areas</div>
</a>
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<li class='active' role='presentation'>
<a href='project.html'>
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<div class='text'>Projects</div>
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<div class='text'>Publications</div>
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<div class='text'>Teaching</div>
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<div class='col-md' style="float:none;margin:auto;">
<img align='center' id='nav-picture-profile' src='image/photo.jpg'>
<h1>Dr. Mehran Goli</h1>
<p class='lead'>Research Fellow, Uni-Bremen/DFKI</p>
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<div class='col-md-2.5' style="float:none;margin:auto;">
<br>
<h3 style='margin-top: 0px'>Contact</h3>
Cyber-Physical Systems
<br>
Bibliothekstraße 5 (MZH)
<br>
28359 Bremen
<br>
Germany
<br>
<i aria-hidden='true' class='fa fa-phone'></i>
+49 421 218 63959
<br>
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<a href='mehran.goli@dfki.de'>mehran.goli@dfki.de</a>
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<a href='mehran@uni-bremen.de'>mehran@uni-bremen.de</a>
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<a href='mehran.golii@gmail.com'>mehran.golii@gmail.com</a>
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<a href='https://www-cps.hb.dfki.de/about/staff/mego01' target='_blank'>DFKI</a>
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<a href='https://scholar.google.com/citations?hl=en&user=mGk9o2kAAAAJ' target='_blank'>Google Scholar</a>
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<a href='https://github.com/mehrangoli' target='_blank'>GitHub</a>
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<a href='https://dblp.uni-trier.de/pid/141/0585.html' target='_blank'>dblp</a>
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<p> <img src="image/versys.jpeg" align="left" alt="ESL" style="width:150px;height:150px;margin-right:15px;margin-top:-15px;">
<font size="4"><b>VerSys: A Sound Verification Platform for Early Software Development for RISC-V based Systems (May 2021 - Now)</b></font> <br>
The aim of the VerSys project is to develop a consistent platform for early software development based on RISC-V technology, an instruction set architecture for microprocessors which has been developed in recent years and which is open source and free of licensing costs or royalties.
In order to take advantage of the many benefits of RISC-V, a virtual prototype will be developed into a flexible and consistent development platform. This allows the software in RISC-V-based systems to be developed parallel to the hardware, which saves development time and costs.
The application areas of VerSys can be found wherever embedded and cyber-physical systems are used, from resource-saving lightweight systems in the smart home setting to computing-intensive applications with AI support
in the automotive sector.</p>
</a>
(<a href="https://www-cps.hb.dfki.de/research/projects/VerSys" target="_blank">Source</a>)
<br>
<a class="list-group-item"><i aria-hidden="true"></i>
<p> <img src="image/SATiSFy" align="left" alt="ESL" style="width:150px;height:150px;margin-right:15px;margin-top:-15px;">
<font size="4"><b>SATiSFy: Timely Validation of Safey and Security Requirements in Autonomous Vehicles (Jan 2020- Apr 2021)</b></font> <br>
The aim of the project is to develop techniques to elicit requirements for systems to control autonomous vehicles, and validate them in a timely fashion, such that the necessary safety and security requirements can be specified uniformly for a heterogeneous and redundant multi-component system on both hardware and software level, and be validated even before the final integration test.
<br>
A key challenge for autonomous driving is to ensure the safety and security of all parties. This applies to both the protection of the environment from a malfunction of the vehicle (safety) as well as the protection of the vehicle against unauthorized manipulation from outside (security). Both aspects are not independent of each other, they are often closely interlinked: manipulations of the vehicle can lead to the failure of individual components and thus to the vehicle's malfunction; conversely, errors that occur in program components make it possible for the attacker to carry out manipulations of the vehicle. As part of the BMBF project SATiSFy, the Bremen site (CPS) is working on methods and techniques in order to be able to collect and formally validate safety and security requirements at the hardware as well as the software level, even before the final system integration. A framework for safety and security architectures is developed in order to be able to check these during development time and at system runtime. Existing security architectures are modified and integrated in such a way that, in the overall context of the framework, by making use of formal arguments and composition a sufficient statement about the achieved security, resilience or the risks against intentional attacks and unintentional actions becomes possible.</p>
</a>
(<a href="https://www-cps.hb.dfki.de/research/projects/SATiSFy" target="_blank">Source</a>)
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<a class="list-group-item">
<p> <img src="image/SecRec.jpg" align="left" alt="ESL" style="width:150px;height:150px;margin-right:15px;margin-top:-15px;">
<font size="4"><b>SecRec: Security by Reconfiguration - Physikalische Sicherheit durch dynamische Hardware-Rekonfiguration (Oct 2018 - Dec 2019)</b></font><br>
Field-programmable gate arrays are a highly efficient platform for cryptographic hardware implementations. Despite of their benefits, security-critical component on FPGA devices need to be protected against various powerful physical attacks, such as side-channel analysis, fault injection attacks, and classical reverse engineering. Therefore, this projects investigates new strategies and methods based on the various reconfiguration features of modern FPGAs to develop effective protection mechanisms against the aforementioned attack vectors. In this context, SecRec aims to identify novel solutions to the fundamental problem that (cryptographic) hardware implementations are realized as static circuits, whose structures can be easily characterized by a (profiling) attacker.</p>
</a>
(<a href="https://www-cps.hb.dfki.de/research/projects/SecRec" target="_blank">Source</a>)
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