PCBend: Light Up Your 3D Shapes With Foldable Circuit Boards

Accompanying repository for the article published in ACM Transactions on Graphics (SIGGRAPH 2023), with doi:10.1145/3592411.

Authors: M. Freire*¹, M. Bhargava*², C. Schreck¹, P.-A. Hugron¹, B. Bickel², S. Lefebvre¹ (* joint first authors)

Affiliations:

• ¹ Université de Lorraine, CNRS, Inria, LORIA, France
• ² ISTA (Institute of Science and Technology Austria), Austria

Please also check the following:

• Project page
• Submission video
• Submission data

Clone, install and compile

The repository has been tested on Ubuntu 20.04, 22.04 and Debian 12.

Before cloning the repository you should install the following apt packages:

sudo apt update
sudo apt install gawk libgl1-mesa-dev freeglut3-dev zlib1g-dev libxrandr-dev libxinerama-dev libxcursor-dev libjpeg-dev libpng-dev libxi-dev libblas-dev

To clone the repository and its submodules run:

git clone https://github.com/mfremer/pcbend.git
git submodule update --init

You can setup and build the whole project by running the following bash scripts:

./setup.sh <#jobs>
./build.sh <#jobs>

where #jobs is passed to cmake's -j flag, with default value 1.

Structure

The repository contains two main folders:

• data/: contains data necessary to the execution of the pipeline.
  • data/meshes/: contains input mesh files in .off format
  • data/modules/: contains module (electronic component) information
  • data/configs/: contain preset settings for the pipeline
  • data/results/: folder where output files are written
• pipeline/: contains the source code of the pipeline, each part separated into its own folder.

Running the pipeline

The generate.sh bash script is used to run the whole pipeline with a single command. Running it without any arguments explains how to use it.

$ generate.sh
> Usage: ./generate.sh MESH CONFIG #PARALLEL "CONN_SFIDS"
> AVAILABLE MESHES:  <mesh-list>
> AVAILABLE CONFIGS: <config-list>

Arguments:

• MESH: any name listed after AVAILABLE MESHES
• CONFIG: any name listed after AVAILABLE CONFIGS
• #PARALLEL: controls the number of faces processed in parallel (1 by default)
• "CONN_SFIDS": advanced parameter controlling the position of the connector in the PCB ("" by default, see Advanced use)

When run, the script displays the input information for verification and asks for confirmation before proceeding. The listed output directory will contain all files generated by the pipeline.

$ ./generate.sh icosa-020 small-dihedral 8 "14"
> PIPELINE
> Mesh         ./data/meshes/icosa-020.off
> Config       ./data/configs/small-dihedral.cfg
> Connector(s) 14
> #Parallel    8
> Output in    ./data/results/icosa-020_small-dihedral
> Continue? (Y/N): 

Please read the warnings section before running the pipeline.

Configurations

Currently the following configurations are available: big-dihedral, big-perimeter, small-dihedral, small-perimeter and default (alias for small-dihedral).

Any configuration with small in the name uses 1515 LEDs, any one with big uses 5050 LEDs. dihedral or perimeter decides the heuristic used for the unfolder. Different heuristics can lead to different numbers of patches in the unfolding (see article for more details).

Output

The output folder will contain the following folders and files:

• faces/: .fis files containing raw placement and routing information
• svgs/: contains the output of the pipeline, a set of svg files per patch (_pX), an svg per PCB layer (EdgeCuts, FCu, BCu...)
• svgs/*.pos: used for pick & place component assembly
• svgs/*_PTH.drl: drill file for the PCB
• *.led + *.map: used for LED control
• *.sheet: output of the unfolder
• _chamfer.off: chamfered mesh for 3d printing
• log.txt: log of the pipeline execution

A word of warning

Execution times can be very long for low values of #Parallel in the largest examples (few minutes to more than an hour). We recommend setting its value to a few less than the number of the CPUs in your machine.

The script gen_examples.sh <#jobs> runs the pipeline sequentially on all default examples with both small and big LEDs, with the best heuristic for each model. Running this script might take multiple hours, even with a large <#jobs> value.

Behavior can be unstable when interrupting (e.g. Ctrl-C) due in part to the multiple subshells spawned by the script. We recommend letting the pipeline run fully even if you made a mistake in the arguments. gen_examples.sh can be interrupted when the script asks for confirmation between examples.

Generating Gerber files

Gerber files are generated from the svg files created by the pipeline using KiCad 6's Import Graphics (Shift-Ctrl-F) feature implemented in Pcbnew, accessible through the menus File > Import > Grapnics.... The recent release of KiCad 7 made changes to this feature breaking compatibility with our files, make sure to use KiCad 6. In the Import Vector Graphics File window, make sure to uncheck Interactive Placement to align all layers properly. Each svg file representing a layer of the PCB should be imported to the corresponding Pcbnew Graphic Layer. Please check the submission data for Gerber files generated this way.

Advanced use

IMPORTANT: read before fabrication

Our PCBs are all 0.6mm thick. We passed our orders with PCBWay, using the default settings for standard PCB on the website (https://www.pcbway.com/orderonline.aspx), except for the PCB thickness which should be 0.6mm.

Different PCB thicknesses will result in different bending angles for the hinges according to their length. Our experiments were carried out exclusively for this specific thickness. Breakages might occur at the same bending angles with thicker PCBs.

The PCBs are designed to be milled with a 1.0mm diameter drill bit, larger bits will not work.

The PCB contour is a complicated shape due to our hinges, and copper traces are close to the border. We suggest that you discuss with your manufacturer how to stabilize the PCB so that it does not move during milling and no traces are damaged. We found that keeping the panel connected to the PCB with breakable tabs worked well in practice.

We used the PCBWay assembly service for all objects. We used the following components:

• LEDs: Inolux IN-PI15TAT5R5G5B (SMD Addressable RGB LED 0505, 1515 metric), Replaceable with SK6805-EC15 1515 RGB Adressable LED
• Capacitor: Samsung Electro-Mechanics CL10B104JB8NNNC (Multilayer Ceramic Capacitors MLCC - SMD/SMT 100nF+/-5% 50V X7R 1 0603, 1608 metric), Replaceable with any capacitor with the same specifications
• Connector: PinHeader 1x04 P2.54mm Vertical

Pin #1 of the LED is marked by a small "1" in the silkscreen layer.

Once fabricated, make sure to check the what pin corresponds to what in the connector. The pins are in the following order: VCC, DATA IN, GND, DATA OUT. The VCC pin is the one that connects to the top copper plane (where the components are soldered). Be sure to check the KiCad files before connecting the PCB. The DATA OUT pin is only useful if you want to chain multiple PCBs together.

Dependencies

The project depends on the following libraries (see pipeline/third-party/):

• LibSL
• libigl
• Clipper (version 1)
• Concorde TSP solver
• (a slight modification of the) Discorde TSP API for Concorde
• HLBFGS
• box2d
• CDT

Citation

@article{10.1145/3592411,
  author = {Freire, Marco and Bhargava, Manas and Schreck, Camille and Hugron, Pierre-Alexandre and Bickel, Bernd and Lefebvre, Sylvain},
  title = {PCBend: Light Up Your 3D Shapes With Foldable Circuit Boards},
  year = {2023},
  issue_date = {August 2023},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  volume = {42},
  number = {4},
  issn = {0730-0301},
  url = {https://doi.org/10.1145/3592411},
  doi = {10.1145/3592411},
  journal = {ACM Trans. Graph.},
  month = {jul},
  articleno = {142},
  numpages = {16},
  keywords = {automated placement and routing, PCB design, PCB bending, 3D electronics}
}

License

This source code is licensed under the GPLv3, see LICENSE.