PIC18F47Q10: Getting started with the CLC on PIC18 -> Using CLCs to Create a Data Signal Modulator -> MCC Generated code

Objective:

The PIC18F47Q10 features 8 Configurable Logic Cell (CLC) peripherals that can be used to implemenmt various logic functions. This example shows an initialization of the CLC in the JK flip-flop with R mode and AND-OR mode, that enables the implementation of a Data Signal Modulator (DSM) with timings controlled from the CCP peripheral.

Related Documentation

Existing application notes or tech briefs that are related to the subject:

• TB3273 - Getting Started with CLC on PIC18

• AN2133 - Extending PIC® MCU Capabilities Using CLC

• TB3133 – Configurable Logic Cell on PIC® Microcontrollers

• AN2805 - Robust Debouncing with Core Independent Peripherals

• DS41631B - Configurable Logic Cell Tips ’n Tricks

• AN2912 - Using CLCs in Real-Time Applications

• AN1606 - Using the Configurable Logic Cell (CLC) to Interface a PIC16F1509 and WS2811 LED Driver

• 20007 CIP1 - Applying Configurable Logic Cell CLC to Interconnect Peripheral Functions

• PIC18F-Q10 Family Product Page

• PIC18F47Q10 Data Sheet

• PIC18F47Q10 Code Examples on GitHub

Software Used

• MPLAB® X IDE 5.30 or newer (microchip.com/mplab/mplab-x-ide)
• MPLAB® XC8 2.10 or a newer compiler (microchip.com/mplab/compilers)
• MPLAB® Code Configurator (MCC) 3.95.0 or newer (microchip.com/mplab/mplab-code-configurator)
• MPLAB® Code Configurator (MCC) Device Libraries PIC10 / PIC12 / PIC16 / PIC18 MCUs (microchip.com/mplab/mplab-code-configurator)
• Microchip PIC18F-Q Series Device Support (1.4.109) or newer (packs.download.microchip.com/)

Hardware Used

• PIC18F47Q10 Curiosity Nano (DM182029)

Setup

The following configurations must be made for this project:

• Timer 2 frequency = 1 MHz (1 us period)
• Timer 4 frequency = 500 kHz (2 us period)
• Timer 6 frequency = 62.5 kHz (16 us period)
• CCP1 has as source Timer6 and duty-cycle = 50%

CLC Configuration:

• CLC1 is set up as JK flip-flop

• CLC2 is set up JK flip flop

• CLC3 is set up as AND-OR

I/O configurations:

Pin	Configuration
RA2	Digital Output
RA3	Digital Output
RB3	Digital Output
RB0	Digital Output

This setup will create an internal connection as depicted:

Operation

Run the codegenerated by MCC, the following signals are to be seen on the oscilloscope:

In the figure below it is depicted the all the CLCs outputs and the CCP1 output side by side to show how this configuration implements DSM function:

• Signal 1 (Yellow) is CCP1 output
• Signal 2 (Green) is CLC1 output
• Signal 3 (Blue) is CLC3 output
• Signal 4 (Red) is CLC2 output

Summary

This project showcases how the Core Independent Peripherals (CIPs) on the new PIC18-Q10 can be used to create an Data Signal Modulator (DSM). This example shows an initialization of the CLC in the JK flip-flop with R mode and AND-OR mode, that enables this implementation. The CLC is one of the most versatile peripherals in the PIC arsenal, and this example proves that the user can implement more modules with its help.