<atomic>: Fix ARM64EC and CHPE codegen

[StephanTLavavej]

This mirrors @mcfi's MSVC-PR-511288 as of Iteration 10, fixing VSO-1918426 which tracks the following issues reported internally by Geoffrey Antos:

1. std::atomic<T>::load() is still generating the original/slow ldr+barrier instructions and not the lda[p]r instructions intended by MSVC-PR-449792 / <atomic>: Improve ARM64 performance #3399.
2. Neither overload of std::atomic<T>::load() appears to guarantee sequential consistency when requested for ARM64 CHPE builds.
3. std::atomic_thread_fence() does not appear to guarantee the requested ordering for CHPE builds (other than for std::memory_order_seq_cst).
4. (Performance) On CHPE builds, std::atomic<T>::exchange(), std::atomic<T>::compare_exchange_*() and std::atomic<T>::fetch_*() appear to force sequentially consistent behavior.