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X86MachineInstructionRaiserUtils.cpp
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X86MachineInstructionRaiserUtils.cpp
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//===-- X86MachineInstructionRaiserUtils.cpp ---------------------*- C++-*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the various utility/helper functions declared in
// X86MachineInstructionRaiser class for use by llvm-mctoll.
//
//===----------------------------------------------------------------------===//
#include "IncludedFileInfo.h"
#include "InstMetadata.h"
#include "X86MachineInstructionRaiser.h"
#include "X86RaisedValueTracker.h"
#include "X86RegisterUtils.h"
#include "llvm-mctoll.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/Object/ELF.h"
#include "llvm/Object/ELFObjectFile.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include <X86InstrBuilder.h>
#include <X86Subtarget.h>
#include <iterator>
#define DEBUG_TYPE "mctoll"
using namespace llvm::mctoll;
using namespace llvm::mctoll::X86RegisterUtils;
Value *X86MachineInstructionRaiser::getMemoryRefValue(const MachineInstr &MI) {
const MCInstrDesc &MIDesc = MI.getDesc();
unsigned int Opcode = MI.getOpcode();
int LoadOrStoreOpIndex = -1;
// Get index of memory reference in the instruction.
int MemoryRefOpIndex = getMemoryRefOpIndex(MI);
// Should have found the index of the memory reference operand
assert(MemoryRefOpIndex != -1 && "Unable to find memory reference "
"operand of a load/store instruction");
X86AddressMode MemRef = llvm::getAddressFromInstr(&MI, MemoryRefOpIndex);
// Get the operand whose value is stored to memory or that is loaded from
// memory.
if (MIDesc.mayStore()) {
// If the instruction stores to stack, find the register whose value is
// being stored. It would be the operand at offset
// MemRefOperandStartIndex + X86::AddrNumOperands
LoadOrStoreOpIndex = MemoryRefOpIndex + X86::AddrNumOperands;
} else if (MIDesc.mayLoad()) {
// If the instruction loads to memory to a register, it has 1 def.
// Operand 0 is the loadOrStoreOp.
assert(((MIDesc.getNumDefs() == 0) || (MIDesc.getNumDefs() == 1)) &&
"Instruction that loads from memory expected to have only "
"one target");
if (MIDesc.getNumDefs() == 1) {
LoadOrStoreOpIndex = 0;
assert(MI.getOperand(LoadOrStoreOpIndex).isReg() &&
"Target of instruction that loads from "
"memory expected to be a register");
} else if (!MIDesc.isCompare() && !MIDesc.isCall()) {
switch (getInstructionKind(Opcode)) {
case InstructionKind::DIVIDE_MEM_OP:
case InstructionKind::LOAD_FPU_REG:
case InstructionKind::SSE_COMPARE_RM:
case InstructionKind::BIT_TEST_OP:
break;
default:
MI.print(errs());
assert(false && "Encountered unhandled memory load instruction");
}
}
} else {
MI.print(errs());
assert(false && "Encountered unhandled instruction that is not load/store");
}
Value *MemoryRefValue = nullptr;
if (MemRef.BaseType == X86AddressMode::RegBase) {
// If it is a stack reference, allocate a stack slot in case the current
// memory reference is new. Else get the stack reference using the
// stackslot index of the previously known stack ref.
uint64_t BaseSupReg = find64BitSuperReg(MemRef.Base.Reg);
if (BaseSupReg == x86RegisterInfo->getStackRegister() ||
BaseSupReg == x86RegisterInfo->getFramePtr()) {
MemoryRefValue = getStackAllocatedValue(MI, MemRef, false);
// If memory operand has an index register with possibly a non-zero scale
// value, add the value represented by IndexReg*Scale to MemoryRefValue.
if (MemRef.IndexReg != X86::NoRegister) {
assert((MemoryRefValue != nullptr) &&
"Unexpected null value of stack or base pointer register");
Type *MemRefValTy = MemoryRefValue->getType();
assert((MemRefValTy->isPointerTy() ||
(MemRefValTy->isIntegerTy() &&
MemRefValTy->getIntegerBitWidth() == 64)) &&
"Unexpected non-pointer type of a stack allocated value");
// Convert MemRefValue to integer
LLVMContext &Ctx(MF.getFunction().getContext());
Type *CastTy = Type::getInt64Ty(Ctx);
BasicBlock *RaisedBB = getRaisedBasicBlock(MI.getParent());
Value *MemRefValAddr;
if (MemRefValTy->isPointerTy()) {
MemRefValAddr =
new PtrToIntInst(MemoryRefValue, CastTy, "", RaisedBB);
} else {
MemRefValAddr = MemoryRefValue;
}
unsigned ScaleAmt = MemRef.Scale;
// IndexReg * Scale
Value *IndexVal = getPhysRegValue(MI, MemRef.IndexReg);
// Cast IndexRegVal as 64-bit integer, if needed.
IndexVal = getRaisedValues()->castValue(IndexVal, CastTy, RaisedBB);
// Generate mul instruction based on Scale value
switch (ScaleAmt) {
case 0:
assert(false && "Unexpected zero-value of scale in memory operand");
break;
case 1:
break;
default: {
Value *ScaleAmtValue = ConstantInt::get(CastTy, ScaleAmt);
Instruction *MulInst = BinaryOperator::CreateMul(
ScaleAmtValue, IndexVal, "sc-m", RaisedBB);
IndexVal = MulInst;
} break;
}
// MemoryRefValue + IndexReg*Scale
Instruction *AddInst = BinaryOperator::CreateAdd(
MemRefValAddr, IndexVal, "idx-a", RaisedBB);
// Propagate any rodata related metadata
getRaisedValues()->setInstMetadataRODataIndex(MemoryRefValue, AddInst);
// Cast the computed address back to MemRefValTy
MemoryRefValue =
getRaisedValues()->castValue(AddInst, MemRefValTy, RaisedBB);
}
}
// Handle PC-relative addressing.
// NOTE: This tool now raises only shared libraries and executables -
// NOT object files. So, instructions with 0 register (which typically
// are seen in a relocatable object file for the linker to patch) are
// not expected to be encountered.
else if (BaseSupReg == X86::RIP) {
MemoryRefValue = createPCRelativeAccesssValue(MI);
}
// If this is neither a stack reference nor a pc-relative access, get the
// associated memory address expression value.
if (MemoryRefValue == nullptr) {
Value *MemRefValue = getMemoryAddressExprValue(MI);
MemoryRefValue = MemRefValue;
}
} else {
// TODO : Memory references with BaseType FrameIndexBase
// (i.e., not RegBase type)
outs() << "****** Unhandled memory reference in instruction\n\t";
LLVM_DEBUG(MI.dump());
outs() << "****** reference of type FrameIndexBase";
}
assert(MemoryRefValue != nullptr &&
"Unable to construct memory referencing value");
return MemoryRefValue;
}
Value *X86MachineInstructionRaiser::loadMemoryRefValue(
const MachineInstr &MI, Value *MemRefValue, unsigned int MemoryRefOpIndex,
Type *SrcTy) {
X86AddressMode MemRef = llvm::getAddressFromInstr(&MI, MemoryRefOpIndex);
uint64_t BaseSupReg = find64BitSuperReg(MemRef.Base.Reg);
bool IsPCRelMemRef = (BaseSupReg == X86::RIP);
// Load the value from memory location of MemRefValue.
// MemRefVal is either an AllocaInst (stack access), GlobalValue (global
// data access), an effective address value, element pointer or select
// instruction.
assert((isa<AllocaInst>(MemRefValue) || isEffectiveAddrValue(MemRefValue) ||
isa<GlobalValue>(MemRefValue) || isa<SelectInst>(MemRefValue) ||
isa<GetElementPtrInst>(MemRefValue) ||
MemRefValue->getType()->isPointerTy()) &&
"Unexpected type of memory reference in SSE conversion instruction");
// Assume that MemRefValue represents a memory reference location and hence
// needs to be loaded from.
bool LoadFromMemrefValue = true;
// Following are the exceptions when MemRefValue needs to be considered as
// memory content and not as memory reference.
if (IsPCRelMemRef) {
// If it is a PC-relative global variable with an initializer, it is memory
// content and should not be loaded from.
if (auto *GV = dyn_cast<GlobalVariable>(MemRefValue))
LoadFromMemrefValue = !(GV->hasInitializer());
// If it is not a PC-relative constant expression accessed using
// GetElementPtrInst, it is memory content and should not be loaded from.
else {
const ConstantExpr *CExpr = dyn_cast<ConstantExpr>(MemRefValue);
if (CExpr != nullptr) {
LoadFromMemrefValue =
(CExpr->getOpcode() == Instruction::GetElementPtr);
}
}
}
if (LoadFromMemrefValue) {
BasicBlock *RaisedBB = getRaisedBasicBlock(MI.getParent());
// If it is an effective address value or a select instruction, convert it
// to a pointer to load register type.
PointerType *PtrTy = PointerType::get(SrcTy, 0);
if ((isEffectiveAddrValue(MemRefValue)) || isa<SelectInst>(MemRefValue)) {
IntToPtrInst *ConvIntToPtr = new IntToPtrInst(MemRefValue, PtrTy);
// Set or copy rodata metadata, if any
getRaisedValues()->setInstMetadataRODataIndex(MemRefValue, ConvIntToPtr);
RaisedBB->getInstList().push_back(ConvIntToPtr);
MemRefValue = ConvIntToPtr;
}
assert(MemRefValue->getType()->isPointerTy() &&
"Pointer type expected in SSE conversion instruction");
// Cast the pointer to match the size of memory being accessed by the
// instruction, as needed.
MemRefValue = getRaisedValues()->castValue(MemRefValue, PtrTy, RaisedBB);
// Load the value from memory location
LoadInst *LdInst =
new LoadInst(SrcTy, MemRefValue, "memload", false, Align());
LdInst = getRaisedValues()->setInstMetadataRODataContent(LdInst);
RaisedBB->getInstList().push_back(LdInst);
return LdInst;
}
// MemRefValue already represents the global value loaded from
// PC-relative memory location. It is incorrect to generate an
// additional load of this value. It should be directly used.
return MemRefValue;
}
// Delete noop instructions
bool X86MachineInstructionRaiser::deleteNOOPInstrMI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
MachineInstr &MI = *MBBI;
auto Opcode = MI.getOpcode();
if (isNoop(Opcode) || Opcode == X86::INT3) {
MBB.remove(&MI);
return true;
}
return false;
}
bool X86MachineInstructionRaiser::deleteNOOPInstrMF() {
bool Modified = false;
for (MachineBasicBlock &MBB : MF) {
// MBBI may be invalidated by the raising operation.
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
while (MBBI != E) {
MachineBasicBlock::iterator NMBBI = std::next(MBBI);
Modified |= deleteNOOPInstrMI(MBB, MBBI);
MBBI = NMBBI;
}
}
return Modified;
}
bool X86MachineInstructionRaiser::unlinkEmptyMBBs() {
bool Modified = false;
std::set<unsigned> EmptyMBBNos;
// Collect empty basic block numbers
for (MachineBasicBlock &MBB : MF) {
if (MBB.empty())
EmptyMBBNos.insert(MBB.getNumber());
}
// Get rid of any empty MachineBasicBlocks
if (!EmptyMBBNos.empty()) {
for (auto MBBNo : EmptyMBBNos) {
MachineBasicBlock *DelMBB = MF.getBlockNumbered(MBBNo);
// Transfer all successors of DelMBB as successors of each of the
// predecessors of DelMBB.
if (DelMBB->pred_size() > 0) {
for (auto *DelMBBPred : DelMBB->predecessors()) {
DelMBBPred->transferSuccessors(DelMBB);
}
} else {
// If DelMBB does not have any predecessors, successors of DelMBB would
// not be deleted since transferAllSuccessors will not be called. So, we
// need to explicitly delete all successors of DelMBB.
for (auto *DelMBBSucc : DelMBB->successors()) {
DelMBB->removeSuccessor(DelMBBSucc);
}
}
// Do not delete DelMBB
}
Modified = true;
}
return Modified;
}
// Return the Type of the physical register.
Type *X86MachineInstructionRaiser::getPhysRegType(unsigned int PReg) {
LLVMContext &Ctx(MF.getFunction().getContext());
if (is64BitPhysReg(PReg))
return Type::getInt64Ty(Ctx);
if (is32BitPhysReg(PReg))
return Type::getInt32Ty(Ctx);
if (is16BitPhysReg(PReg))
return Type::getInt16Ty(Ctx);
if (is8BitPhysReg(PReg))
return Type::getInt8Ty(Ctx);
if (isSSE2Reg(PReg)) {
// Since float- and double types both use the same width SSE registers, we
// can't check which one is correct. Use getPhysSSERegType with a
// BitPrecision argument
return Type::getInt128Ty(Ctx);
}
assert(false && "Immediate operand of unknown size");
return nullptr;
}
Type *X86MachineInstructionRaiser::getPhysSSERegType(unsigned int PhysReg,
uint8_t BitPrecision) {
LLVMContext &Ctx(MF.getFunction().getContext());
assert(isSSE2Reg(PhysReg) && "Expected SSE2 register");
switch (BitPrecision) {
case 64:
return Type::getDoubleTy(Ctx);
case 32:
return Type::getFloatTy(Ctx);
default:
llvm_unreachable("Unhandled bit precision");
return nullptr;
}
}
Type *X86MachineInstructionRaiser::getImmOperandType(const MachineInstr &MI,
unsigned int OpIndex) {
LLVMContext &Ctx(MI.getMF()->getFunction().getContext());
MachineOperand Op = MI.getOperand(OpIndex);
assert(Op.isImm() && "Attempt to get size of non-immediate operand");
uint8_t ImmSize = X86II::getSizeOfImm(MI.getDesc().TSFlags);
switch (ImmSize) {
case 8:
return Type::getInt64Ty(Ctx);
case 4:
return Type::getInt32Ty(Ctx);
case 2:
return Type::getInt16Ty(Ctx);
case 1:
return Type::getInt8Ty(Ctx);
default:
llvm_unreachable("Immediate operand of unknown size");
}
}
uint8_t
X86MachineInstructionRaiser::getPhysRegOperandSize(const MachineInstr &MI,
unsigned int OpIndex) {
MachineOperand Op = MI.getOperand(OpIndex);
assert(Op.isReg() && "Attempt to get size of non-register operand");
return (getPhysRegSizeInBits(Op.getReg()) / sizeof(uint64_t));
}
Type *X86MachineInstructionRaiser::getPhysRegOperandType(const MachineInstr &MI,
unsigned int OpIndex) {
MachineOperand Op = MI.getOperand(OpIndex);
assert(Op.isReg() && "Attempt to get type of non-register operand");
LLVMContext &Ctx(MI.getMF()->getFunction().getContext());
auto PReg = Op.getReg();
auto RegSzInBits = getRegisterInfo()->getRegSizeInBits(PReg, machineRegInfo);
assert(RegSzInBits > 0 && "Non-zero register size expected");
if (isGPReg(PReg)) {
return Type::getIntNTy(Ctx, RegSzInBits);
}
if (isSSE2Reg(PReg)) {
return getRaisedValues()->getSSEInstructionType(MI, RegSzInBits, Ctx);
}
llvm_unreachable("Unhandled register type encountered");
}
bool X86MachineInstructionRaiser::isPushToStack(const MachineInstr &MI) const {
return instrNameStartsWith(MI, "PUSH") || instrNameStartsWith(MI, "ENTER");
}
bool X86MachineInstructionRaiser::isPopFromStack(const MachineInstr &MI) const {
return instrNameStartsWith(MI, "POP") || instrNameStartsWith(MI, "LEAVE");
}
bool X86MachineInstructionRaiser::isEffectiveAddrValue(Value *Val) {
if (isa<LoadInst>(Val))
return true;
// A call may return a pointer that can be considered an effective address.
if (isa<CallInst>(Val))
return true;
// An instruction that casts a pointer value may be considered as an effective
// address.
if (isa<PtrToIntInst>(Val)) {
return (dyn_cast<PtrToIntInst>(Val)->getSrcTy()->isPointerTy());
}
if (isa<BinaryOperator>(Val)) {
BinaryOperator *BinOpVal = dyn_cast<BinaryOperator>(Val);
if (BinOpVal->isBinaryOp(BinaryOperator::Add) ||
BinOpVal->isBinaryOp(BinaryOperator::Mul)) {
return true;
}
}
// Consider an argument of integer type to be an address value type.
if (Val->getType()->isIntegerTy() && (Val->getName().startswith("arg")))
return true;
return false;
}
bool X86MachineInstructionRaiser::recordDefsToPromote(unsigned PhysReg,
unsigned MBBNo,
Value *Alloca) {
reachingDefsToPromote.insert(std::make_tuple(PhysReg, MBBNo, Alloca));
return true;
}
// Return the MachineInstr if MBB has a definition of PhysReg in the instruction
// range [StopInst, StartMI) where StopInst is the last instance of instruction
// with the opcode property StopAtInstProp. For example, if StopAtInstProp is
// MCID::Call, this function returns the instruction that defined PhysReg in the
// range [LCI, StartInst) where LCI is the last call instruction in MBB.
//
// If StartMI is nullptr, the range searched in [StopInst, BlockEndInst].
const MachineInstr *X86MachineInstructionRaiser::getPhysRegDefiningInstInBlock(
int PhysReg, const MachineInstr *StartMI, const MachineBasicBlock *MBB,
unsigned StopAtInstProp, bool &HasStopInst) {
// Walk backwards starting from the instruction before StartMI
HasStopInst = false; // default value
unsigned SuperReg = find64BitSuperReg(PhysReg);
auto InstIter =
(StartMI == nullptr) ? MBB->rend() : StartMI->getReverseIterator();
for (const MachineInstr &MI : make_range(++InstIter, MBB->rend())) {
// Stop after the instruction with the specified property in the block
if (MI.hasProperty(StopAtInstProp)) {
HasStopInst = true;
break;
}
// Look if PhysReg is either an explicit or implicit register def
if (MI.getNumDefs() > 0) {
for (auto MO : MI.operands()) {
// Consider only the register operand
if (MO.isReg() && MO.isDef()) {
Register MOReg = MO.getReg();
// If it is a physical register other than EFLAGS
if (MOReg != X86::EFLAGS && Register::isPhysicalRegister(MOReg)) {
if (SuperReg == find64BitSuperReg(MOReg))
return &MI;
}
}
}
}
}
return nullptr;
}
// FPU Access functions
void X86MachineInstructionRaiser::pushFPURegisterStack(Value *Val) {
assert(Val->getType()->isFloatingPointTy() &&
"Attempt to push non-FP type value on FPU register stack");
assert((FPUStack.TOP < FPUSTACK_SZ) && (FPUStack.TOP >= 0) &&
"Incorrect initial FPU Register Stack top in push");
int8_t PushIndex = (FPUSTACK_SZ + FPUStack.TOP - 1) % FPUSTACK_SZ;
assert((PushIndex < FPUSTACK_SZ) && (PushIndex >= 0) &&
"Incorrect FPU Register Stack index computed in push");
FPUStack.Regs[PushIndex] = Val;
FPUStack.TOP = PushIndex;
}
void X86MachineInstructionRaiser::popFPURegisterStack() {
assert((FPUStack.TOP < FPUSTACK_SZ) && (FPUStack.TOP >= 0) &&
"Incorrect initial FPU Register Stack top in pop");
int8_t PostPopIndex = (FPUSTACK_SZ + FPUStack.TOP + 1) % FPUSTACK_SZ;
assert((PostPopIndex < FPUSTACK_SZ) && (PostPopIndex >= 0) &&
"Incorrect FPU Register Stack index computed in pop");
// Clear the value at current TOP
FPUStack.Regs[FPUStack.TOP] = nullptr;
// Adjust TOP value
FPUStack.TOP = PostPopIndex;
}
// Get value at index
Value *X86MachineInstructionRaiser::getFPURegisterStackValueAt(int8_t Index) {
assert((FPUStack.TOP < FPUSTACK_SZ) && (FPUStack.TOP >= 0) &&
"Incorrect initial FPU Register Stack top in FPU register access");
int8_t AccessIndex = (FPUSTACK_SZ + FPUStack.TOP + Index) % FPUSTACK_SZ;
assert((AccessIndex < FPUSTACK_SZ) && (AccessIndex >= 0) &&
"Incorrect FPU Register Stack index computed in FPU register access");
return FPUStack.Regs[AccessIndex];
}
// Set value at index to val
void X86MachineInstructionRaiser::setFPURegisterStackValueAt(int8_t Index,
Value *Val) {
assert(Val->getType()->isFloatingPointTy() &&
"Attempt to insert non-FP type value in FPU register stack");
assert((FPUStack.TOP < FPUSTACK_SZ) && (FPUStack.TOP >= 0) &&
"Incorrect initial FPU Register Stack top in FPU register access");
int8_t AccessIndex = (FPUSTACK_SZ + FPUStack.TOP + Index) % FPUSTACK_SZ;
assert((AccessIndex < FPUSTACK_SZ) && (AccessIndex >= 0) &&
"Incorrect FPU Register Stack index computed in FPU register access");
FPUStack.Regs[AccessIndex] = Val;
}
Value *X86MachineInstructionRaiser::topFPURegisterStack() {
return getFPURegisterStackValueAt(0);
}
unsigned int
X86MachineInstructionRaiser::find64BitSuperReg(unsigned int PhysReg) {
// No super register for 0 register
if (PhysReg == X86::NoRegister) {
return X86::NoRegister;
}
// Nothing to do if PhysReg is one of EFLAG bits, FPSW, FPCW
if (isEflagBit(PhysReg))
return PhysReg;
if ((PhysReg == X86::FPSW) || (PhysReg == X86::FPCW)) {
return PhysReg;
}
// Nothing to do if PhysReg is a 64-bit register.
if (is64BitPhysReg(PhysReg)) {
return PhysReg;
}
// Return PhysReg if it is an xmm register
if (is64BitSSE2Reg(PhysReg))
return PhysReg;
// The return value.
unsigned int SuperReg;
// Did we find it.
bool SuperRegFound = false;
for (MCSuperRegIterator SuperRegsIter(PhysReg, x86RegisterInfo);
SuperRegsIter.isValid(); ++SuperRegsIter) {
SuperReg = *SuperRegsIter;
if (is64BitPhysReg(SuperReg)) {
assert(SuperRegFound != true && "Expect only one 64-bit super register");
SuperRegFound = true;
}
}
assert(SuperRegFound && "Unsupported register found");
return SuperReg;
}
BasicBlock *
X86MachineInstructionRaiser::getRaisedBasicBlock(const MachineBasicBlock *MBB) {
// Get the BasicBlock corresponding to MachineBasicBlock MBB
auto MapIter = mbbToBBMap.find(MBB->getNumber());
assert(MapIter != mbbToBBMap.end() &&
"Failed to find BasicBlock corresponding to MachineBasicBlock");
BasicBlock *RaisedBB = MapIter->second;
assert((RaisedBB != nullptr) &&
"Encountered null BasicBlock corresponding to MachineBasicBlock");
return RaisedBB;
}
// Construct and return a Value* corresponding to PC-relative memory address
// access. Insert any intermediate values created in the process into
// curBlock.
Value *X86MachineInstructionRaiser::createPCRelativeAccesssValue(
const MachineInstr &MI) {
Value *MemrefValue = nullptr;
// Get index of memory reference in the instruction.
int MemoryRefOpIndex = getMemoryRefOpIndex(MI);
// Should have found the index of the memory reference operand
assert(MemoryRefOpIndex != -1 &&
"Unable to find memory reference operand of a load/store instruction");
X86AddressMode MemRef = llvm::getAddressFromInstr(&MI, MemoryRefOpIndex);
// LLVM represents memory operands using 5 operands
// viz., <opcode> BaseReg, ScaleAmt, IndexReg, Disp, Segment, ...
// The disassembly in AT&T syntax is shown as
// Segment:Disp(BaseReg, IndexReg, ScaleAmt).
// or as
// Segment:[BaseReg + Disp + IndexReg * ScaleAmt]
// in Intel syntax.
// effective address is calculated to be Segment:[BaseReg + IndexReg *
// ScaleAmt + Disp] Segment is typically X86::NoRegister.
assert(MI.getOperand(MemoryRefOpIndex + X86::AddrSegmentReg).getReg() ==
X86::NoRegister &&
"Expect no segment register");
// Construct non-stack memory referencing value
unsigned BaseReg = MemRef.Base.Reg;
unsigned IndexReg = MemRef.IndexReg;
unsigned ScaleAmt = MemRef.Scale;
int Disp = MemRef.Disp;
const MachineOperand &SegRegOperand =
MI.getOperand(MemoryRefOpIndex + X86::AddrSegmentReg);
// For now, we assume default segment DS (and hence no specification of
// Segment register.
assert(SegRegOperand.isReg() && (SegRegOperand.getReg() == X86::NoRegister) &&
"Unhandled memory reference instruction with non-zero segment "
"register");
// Also assume that PC-relative addressing does not involve index register
assert(IndexReg == X86::NoRegister &&
"Unhandled index register in PC-relative memory addressing "
"instruction");
assert(ScaleAmt == 1 && "Unhandled value of scale amount in PC-relative "
"memory addressing instruction");
// Non-stack memory address is supported by this function.
uint64_t BaseSupReg = find64BitSuperReg(BaseReg);
assert(((BaseSupReg == X86::RIP) || (BaseSupReg == X86::NoRegister)) &&
"Base register that is not PC encountered in memory access "
"instruction");
// 1. Get the text section address
int64_t TextSectionAddress = MR->getTextSectionAddress();
assert(TextSectionAddress >= 0 && "Failed to find text section address");
// 2. Get MCInst offset - the offset of machine instruction in the binary
// and instruction size
MCInstRaiser *MCIRaiser = getMCInstRaiser();
uint64_t MCInstOffset = MCIRaiser->getMCInstIndex(MI);
uint64_t MCInstSz = MCIRaiser->getMCInstSize(MCInstOffset);
// 3. Compute the PC-relative offset.
const ELF64LEObjectFile *Elf64LEObjFile =
dyn_cast<ELF64LEObjectFile>(MR->getObjectFile());
assert(Elf64LEObjFile != nullptr &&
"Only 64-bit ELF binaries supported at present.");
auto EType = Elf64LEObjFile->getELFFile().getHeader().e_type;
if ((EType == ELF::ET_DYN) || (EType == ELF::ET_EXEC)) {
uint64_t PCOffset = TextSectionAddress + MCInstOffset + MCInstSz + Disp;
const RelocationRef *DynReloc = MR->getDynRelocAtOffset(PCOffset);
// If there is a dynamic relocation for the PCOffset
if (DynReloc) {
auto DynRelocType = DynReloc->getType();
if ((DynRelocType == ELF::R_X86_64_COPY) ||
(DynRelocType == ELF::R_X86_64_GLOB_DAT)) {
Expected<StringRef> Symname = DynReloc->getSymbol()->getName();
assert(Symname &&
"Failed to find symbol associated with dynamic relocation.");
// Find if a global value associated with symbol name is already
// created
for (GlobalVariable &GV : MR->getModule()->globals()) {
if (GV.getName().compare(Symname.get()) == 0) {
MemrefValue = &GV;
}
}
if (MemrefValue == nullptr) {
// Get all necessary information about the global symbol.
llvm::LLVMContext &Ctx(MF.getFunction().getContext());
DataRefImpl SymbImpl = DynReloc->getSymbol()->getRawDataRefImpl();
// get symbol
auto SymbOrErr = Elf64LEObjFile->getSymbol(SymbImpl);
assert(SymbOrErr && "PC-relative access: Dynamic symbol not found");
// get symbol size
auto *Symb = SymbOrErr.get();
uint64_t SymbSize = Symb->st_size;
GlobalValue::LinkageTypes Lnkg;
switch (Symb->getBinding()) {
case ELF::STB_GLOBAL:
Lnkg = GlobalValue::ExternalLinkage;
break;
default:
assert(false && "Unhandled dynamic symbol");
}
// Check that symbol type is data object, representing a variable or
// array etc.
assert((Symb->getType() == ELF::STT_OBJECT) &&
"Function symbol type expected. Not found");
Type *GlobalValTy = nullptr;
switch (SymbSize) {
case 8:
GlobalValTy = Type::getInt64Ty(Ctx);
break;
case 4:
GlobalValTy = Type::getInt32Ty(Ctx);
break;
case 2:
GlobalValTy = Type::getInt16Ty(Ctx);
break;
case 1:
GlobalValTy = Type::getInt8Ty(Ctx);
break;
default:
assert(false && "Unexpected symbol size");
}
// get symbol value - this is the virtual address of symbol's value
uint64_t SymVirtualAddr = Symb->st_value;
// get the initial value of the global data symbol at symVirtualAddr
// from the section that contains the virtual address
// symVirtualAddr. In executable and shared object files, st_value
// holds a virtual address.
uint64_t SymbVal = 0;
for (section_iterator SecIter : Elf64LEObjFile->sections()) {
uint64_t SecStart = SecIter->getAddress();
uint64_t SecEnd = SecStart + SecIter->getSize();
if ((SecStart <= SymVirtualAddr) && (SecEnd >= SymVirtualAddr)) {
// Get the initial symbol value only if this is not a bss
// section. Else, symVal is already initialized to 0.
if (SecIter->isBSS()) {
Lnkg = GlobalValue::CommonLinkage;
} else {
StringRef SecData = unwrapOrError(
SecIter->getContents(), MR->getObjectFile()->getFileName());
unsigned Index = SymVirtualAddr - SecStart;
const unsigned char *Begin = SecData.bytes_begin() + Index;
char Shift = 0;
while (SymbSize-- > 0) {
// We know this is little-endian
SymbVal = ((*Begin++) << Shift) | SymbVal;
Shift += 8;
}
}
break;
}
}
Constant *GlobalInit;
if (IncludedFileInfo::isExternalVariable(Symname->str())) {
GlobalInit = nullptr;
Lnkg = GlobalValue::ExternalLinkage;
} else {
GlobalInit = (DynRelocType == ELF::R_X86_64_GLOB_DAT)
? ConstantInt::get(GlobalValTy, SymbVal)
: nullptr;
}
auto *GlobalVal = new GlobalVariable(*(MR->getModule()), GlobalValTy,
false /* isConstant */, Lnkg,
GlobalInit, Symname->data());
// Don't use symbSize as it was modified.
GlobalVal->setAlignment(MaybeAlign(Symb->st_size));
GlobalVal->setDSOLocal(true);
MemrefValue = GlobalVal;
}
} else {
assert(false && "Unexpected relocation type referenced in PC-relative "
"memory access instruction.");
}
} else {
MemrefValue = getGlobalVariableValueAt(MI, PCOffset);
}
} else if (EType == ELF::ET_REL) {
const RelocationRef *TextReloc =
MR->getTextRelocAtOffset(MCInstOffset, MCInstSz);
assert(TextReloc &&
"Failed to get dynamic relocation for pc-relative offset");
if (TextReloc->getType() == ELF::R_X86_64_32S) {
Expected<StringRef> Symname = TextReloc->getSymbol()->getName();
assert(Symname &&
"Failed to find symbol associated with text relocation.");
// Find if a global value associated with symbol name is already
// created
for (GlobalVariable &GV : MR->getModule()->globals()) {
if (GV.getName().compare(Symname.get()) == 0) {
MemrefValue = &GV;
}
}
if (MemrefValue == nullptr) {
// Get all necessary information about the text relocation symbol
// which is most likely global.
llvm::LLVMContext &Ctx(MF.getFunction().getContext());
DataRefImpl SymbImpl = TextReloc->getSymbol()->getRawDataRefImpl();
// get symbol
auto SymbOrErr = Elf64LEObjFile->getSymbol(SymbImpl);
assert(SymbOrErr && "PC-relative access: Relocation symbol not found");
// get symbol size
auto *Symb = SymbOrErr.get();
uint64_t SymSize = Symb->st_size;
GlobalValue::LinkageTypes Lnkg;
switch (Symb->getBinding()) {
case ELF::STB_GLOBAL:
Lnkg = GlobalValue::ExternalLinkage;
break;
default:
assert(false && "Unhandled dynamic symbol");
}
// get symbol value - this is the offset from the beginning of the
// section st_shndex identifies.
uint64_t SymVal = Symb->st_value;
uint64_t SymValSecIndex = Symb->st_shndx;
uint8_t SymAlignment = 0;
uint64_t SymInitVal = 0;
if (((SymValSecIndex >= ELF::SHN_LORESERVE) &&
(SymValSecIndex <= ELF::SHN_HIRESERVE)) ||
(SymValSecIndex == ELF::SHN_UNDEF)) {
if (SymValSecIndex == ELF::SHN_COMMON) {
// st_value holds symbol alignment constraints
SymAlignment = SymVal;
Lnkg = GlobalValue::CommonLinkage;
}
} else {
// get the initial value of the global data symbol at offset symVal
// in section with index symValSecIndex
for (section_iterator SecIter : Elf64LEObjFile->sections()) {
if (SecIter->getIndex() == SymValSecIndex) {
StringRef SecData = unwrapOrError(
SecIter->getContents(), MR->getObjectFile()->getFileName());
const unsigned char *Begin = SecData.bytes_begin() + SymVal;
char Shift = 0;
while (SymSize-- > 0) {
// We know this is little-endian
SymInitVal = ((*Begin++) << Shift) | SymInitVal;
Shift += 8;
}
break;
}
}
// REVISIT : Set symbol alignment to be the same as symbol size
// NOTE : Do not use symSize since it has been modified in the while
// loop above.
SymAlignment = Symb->st_size;
}
Type *GlobalValTy = nullptr;
switch (SymAlignment) {
case 8:
GlobalValTy = Type::getInt64Ty(Ctx);
break;
case 4:
GlobalValTy = Type::getInt32Ty(Ctx);
break;
case 2:
GlobalValTy = Type::getInt16Ty(Ctx);
break;
case 1:
GlobalValTy = Type::getInt8Ty(Ctx);
break;
default:
assert(false && "Unexpected symbol size");
}
Constant *GlobalInit;
if (IncludedFileInfo::isExternalVariable(Symname->str())) {
GlobalInit = nullptr;
Lnkg = GlobalValue::ExternalLinkage;
} else {
GlobalInit = ConstantInt::get(GlobalValTy, SymInitVal);
}
auto *GlobalVal = new GlobalVariable(*(MR->getModule()), GlobalValTy,
false /* isConstant */, Lnkg,
GlobalInit, Symname->data());
// Don't use symSize as it was modified.
GlobalVal->setAlignment(MaybeAlign(SymAlignment));
GlobalVal->setDSOLocal(true);
MemrefValue = GlobalVal;
}
} else {
assert(false && "Unexpected relocation type referenced in PC-relative "
"memory access instruction.");
}
} else {
assert(false && "Unhandled binary type. Only object files and shared "
"libraries supported");
}
return MemrefValue;
}
// Promote the ReachingValue of PhysReg defined in DefiningMBB to specified
// stack slot Alloca.
StoreInst *X86MachineInstructionRaiser::promotePhysregToStackSlot(
int PhysReg, Value *ReachingValue, int DefiningMBBNo, Instruction *Alloca) {
StoreInst *StInst = nullptr;
LLVMContext &Ctxt(MF.getFunction().getContext());
assert((ReachingValue != nullptr) &&
"Null incoming value of reaching definition found");
assert(
raisedValues->getInBlockRegOrArgDefVal(PhysReg, DefiningMBBNo).second ==
ReachingValue &&
"Inconsistent reaching defined value found");
assert((ReachingValue->getType()->isIntOrPtrTy() ||
ReachingValue->getType()->isFloatingPointTy() ||
ReachingValue->getType()->isVectorTy()) &&
"Unsupported: Stack promotion of non-integer / non-pointer value");
// Prepare to store this value in stack location.
// Get the size of defined physical register
int DefinedPhysRegSzInBits =
raisedValues->getInBlockPhysRegSize(PhysReg, DefiningMBBNo);
assert(((DefinedPhysRegSzInBits == 128) || (DefinedPhysRegSzInBits == 64) ||
(DefinedPhysRegSzInBits == 32) || (DefinedPhysRegSzInBits == 16) ||
(DefinedPhysRegSzInBits == 8) || (DefinedPhysRegSzInBits == 1)) &&
"Unexpected physical register size of reaching definition ");
// This could simply be set to 64 because the stack slot allocated is
// a 64-bit value.
int StackLocSzInBits =
getPointerElementType(Alloca)->getPrimitiveSizeInBits();
Type *StackLocTy;
if (ReachingValue->getType()->isIntOrPtrTy()) {
// Cast the current value to int64 if needed
StackLocTy = Type::getIntNTy(Ctxt, StackLocSzInBits);
} else if (ReachingValue->getType()->isFloatingPointTy() ||
ReachingValue->getType()->isVectorTy()) {
assert(
StackLocSzInBits == 128 &&
"Expected FP types and vectors to be stored in 128 bit stack location");
StackLocTy = VectorType::get(Type::getInt32Ty(Ctxt), 4, false);
} else {
llvm_unreachable("Unhandled type");
}
BasicBlock *ReachingBB =
getRaisedBasicBlock(MF.getBlockNumbered(DefiningMBBNo));
// get terminating instruction. Add new instructions before
// terminator instruction if one exists.
Instruction *TermInst = ReachingBB->getTerminator();
if (StackLocTy != ReachingValue->getType()) {
if (ReachingValue->getType()->isFloatingPointTy() ||
ReachingValue->getType()->isVectorTy()) {
// Don't cast values stored in SSE registers
ReachingValue = getRaisedValues()->reinterpretSSERegValue(
ReachingValue, StackLocTy, ReachingBB, TermInst);
} else {
CastInst *CInst = CastInst::Create(
CastInst::getCastOpcode(ReachingValue, false, StackLocTy, false),
ReachingValue, StackLocTy);
if (TermInst == nullptr)
ReachingBB->getInstList().push_back(CInst);
else
CInst->insertBefore(TermInst);
ReachingValue = CInst;
}
}
StInst = new StoreInst(ReachingValue, Alloca, false, Align());
if (TermInst == nullptr)
ReachingBB->getInstList().push_back(StInst);
else
StInst->insertBefore(TermInst);
// Construct a list of instructions that use ReachingValue, if it is not a
// Constant or an argument. This list holds instructions that use
// ReachingValue that is neither a Constant nor an argument value and are in
// a basic block other than DefiningMBB.
SmallVector<Instruction *, 4> UsageInstList;
// Nothing to do if ReachingValue is either a Constant or an argument value.
if (isa<Constant>(ReachingValue) ||
ReachingValue->getName().startswith("arg") ||
isa<LoadInst>(ReachingValue))
return StInst;
MachineDominatorTree MDT(MF);
auto *DefiningMBB = MF.getBlockNumbered(DefiningMBBNo);
// Construct instructions that use ReachingValue and are in a basic block
// other than DefiningMBB.
for (auto *U : ReachingValue->users()) {
if (auto *I = dyn_cast<Instruction>(U)) {
if (I->getParent() == ReachingBB)
continue;
// find MBB number from which the instruction was raised
auto InstMBBNo =
std::find_if(std::begin(mbbToBBMap), std::end(mbbToBBMap),
[&](const std::pair<unsigned int, BasicBlock *> &Pair) {