Will have plan to support RISC-V processor? Or how to port to different processor?

[rayeh5]

Will you have plan to support more processors or can provide porting guide.

[pranavsharma]

Not at this time. We welcome contributions.

[pranav-prakash]

The existing arm cross-compile flow gets you 95% of the way there. The only major changes to be made are substituting the SIMD mlas functions with scalar equivalents. Ideally you'd make use of the v-extension but that's still a wip.

For other architectures, so long as your target platform has a c++ compiler it should just compile fine, although you'll probably want to create your own provider backend to take advantage of vectorization.

I'm maintaining a fork that works on riscv. It also supports the gemmini matmul accelerator (a rocc co-processor).

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