Avoid panic from DumpRegister in circuit display

[swernli]

This avoids a panic on empty state that can happen when DumpRegister is called on an empty state vector, such as when generating a circuit without any underlying quantum simulation.

[github-actions]

Benchmark for 5b807cc

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Test	Base	PR	%
Array append evaluation	325.9±1.48µs	328.1±2.36µs	+0.68%
Array literal evaluation	186.8±1.15µs	176.4±1.00µs	-5.57%
Array update evaluation	409.4±2.09µs	409.7±2.43µs	+0.07%
Core + Standard library compilation	19.0±0.33ms	19.3±1.05ms	+1.58%
Deutsch-Jozsa evaluation	5.0±0.04ms	5.1±0.04ms	+2.00%
Large file parity evaluation	33.9±0.11ms	33.9±0.26ms	0.00%
Large input file compilation	12.8±0.30ms	13.0±0.29ms	+1.56%
Large input file compilation (interpreter)	47.5±0.82ms	47.7±0.93ms	+0.42%
Large nested iteration	32.4±0.47ms	33.0±1.00ms	+1.85%
Perform Runtime Capabilities Analysis (RCA) on Deutsch-Jozsa sample	1570.4±39.74µs	1561.9±57.08µs	-0.54%
Perform Runtime Capabilities Analysis (RCA) on large file sample	7.9±0.09ms	7.8±0.18ms	-1.27%
Perform Runtime Capabilities Analysis (RCA) on teleport sample	1435.5±36.88µs	1420.0±46.31µs	-1.08%
Perform Runtime Capabilities Analysis (RCA) on the core and std libraries	28.3±0.30ms	28.1±0.15ms	-0.71%
Teleport evaluation	88.3±5.33µs	89.1±3.70µs	+0.91%