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Fork mem_trans.s to generate ICU stress test #35

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pavelkryukov opened this issue Feb 2, 2017 · 9 comments
Open

Fork mem_trans.s to generate ICU stress test #35

pavelkryukov opened this issue Feb 2, 2017 · 9 comments
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1 Usually one-liner tasks, but may require some deep into infrastructure. good first issue Good task to start with MIPT-MIPS development S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA testing Improves testing coverage

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@pavelkryukov
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pavelkryukov commented Feb 2, 2017 •
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Currently mem_trans.s is designed to test Data Cache Unit, but we might want to test Instruction Cache Unit. So, the new trace should contain non-memory instructions.
@pavelkryukov pavelkryukov added 1 Usually one-liner tasks, but may require some deep into infrastructure. testing Improves testing coverage S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA labels Feb 2, 2017
@ivan23kor ivan23kor self-assigned this Feb 17, 2017
@pavelkryukov
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pavelkryukov commented Feb 17, 2017 •
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@ivan23kor

That is a very simple task although important one. You have to replace all memory instructions to non-memory instructions in copy of mem_trans.s (would be code_trans.s).
MIPS instructions https://github.com/MIPT-ILab/mipt-mips/wiki/MIPS-Instruction-Set. However, our simulator does not support all of them, here is the list of all supported instructions: https://github.com/MIPT-ILab/mipt-mips/blob/master/func_sim/func_instr/func_instr.cpp

@pavelkryukov
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@ivan23kor Please share your progress on this.

@ivan23kor
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ivan23kor commented Feb 28, 2017 via email

@gkorepanov
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I'm sorry for a couple of silly questions:

  1. I'm wondering what are the DCU and ICU?
  2. find haven't gave me any file named mem_trans.s in our repo. Am I missing something?

@igorsmir-ilab
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Hello,

  1. DCU stands for "Data Cache Unit", while ICU means "Instruction Cache Unit". They are also called L1D and L1I, where L1 means "level 1" cache. You may find processor terminology e.g. in section 1.2 of Intel cheatsheet.
  2. I believe @pavelkryukov meant our memory test, which is currently located under tests/samples and called memtrace_based.s, not mem_trans.s.

@pavelkryukov
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Yep, sure I meant memtrace_based.s

@gkorepanov
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I'm really grateful for your explanations and references. I believe it will help me to proceed.

@pavelkryukov
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@gkorepanov Any progress?

@pavelkryukov pavelkryukov mentioned this issue Jun 22, 2017
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@pavelkryukov
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Kamino closed and cloned this issue to MIPT-ILab/mips-traces

@pavelkryukov pavelkryukov added duplicate and removed 1 Usually one-liner tasks, but may require some deep into infrastructure. S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA testing Improves testing coverage labels Oct 2, 2017
@pavelkryukov pavelkryukov reopened this Sep 27, 2018
@pavelkryukov pavelkryukov added testing Improves testing coverage 1 Usually one-liner tasks, but may require some deep into infrastructure. S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA good first issue Good task to start with MIPT-MIPS development and removed duplicate labels Sep 27, 2018
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