fix instruction synchronization bug on a real RISC-V processor

[sashimi-yzh]

• RISC-V does not guarantee that a stored instruction can be seen by the
  subsequent instruction fetches. This is a case of loading user
  programs in an operating system. The original kernel can run on QEMU.
  But to run on a real RISC-V processor, we should use FENCE.I to let
  subsequent instruction fetches see the stored instructions.

• Fork() will also copy pages containing instructions. We should add a
  FENCE.I before uvmcopy() returns.

• NOTE: The current solution only works for a single-processor system.
  According to the RISC-V manual, for a multiprocess system, we should

  1. copy the code (in exec() or uvmcopy())
  2. execute a FENCE instruciton to let the data stream of other harts
     see the copied code
  3. use IPI to notify other harts to execute a FENCE.I to let their
     instruction stream see the copied code

[kaashoek]

Thanks for the comment, and a good observation. We believe, however, that xv6 already handles this correctly, because the child cannot run until the parent releases the lock of the child and the release has a memory barrier. (We have a short discussion about this at the end of section 9.3 in the text book.)