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Merge pull request f4pga#448 from mcmasterg/fuzzer_tiletype
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fuzzers: name with tile type
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mcmasterg committed Jan 7, 2019
2 parents 069f9f5 + 815c3d4 commit 747a132
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Showing 146 changed files with 20 additions and 20 deletions.
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40 changes: 20 additions & 20 deletions fuzzers/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -24,29 +24,29 @@ all:: 005-tilegrid/run.ok
touch 005-tilegrid/run.ok
endif

$(eval $(call fuzzer,010-lutinit,005-tilegrid))
$(eval $(call fuzzer,011-ffconfig,005-tilegrid))
$(eval $(call fuzzer,012-clbn5ffmux,005-tilegrid))
$(eval $(call fuzzer,013-clbncy0,005-tilegrid))
$(eval $(call fuzzer,014-ffsrcemux,005-tilegrid))
$(eval $(call fuzzer,015-clbnffmux,005-tilegrid))
$(eval $(call fuzzer,016-clbnoutmux,005-tilegrid))
$(eval $(call fuzzer,017-clbprecyinit,005-tilegrid))
$(eval $(call fuzzer,018-clbram,005-tilegrid))
$(eval $(call fuzzer,019-ndi1mux,005-tilegrid))
$(eval $(call fuzzer,010-clb-lutinit,005-tilegrid))
$(eval $(call fuzzer,011-clb-ffconfig,005-tilegrid))
$(eval $(call fuzzer,012-clb-n5ffmux,005-tilegrid))
$(eval $(call fuzzer,013-clb-ncy0,005-tilegrid))
$(eval $(call fuzzer,014-clb-ffsrcemux,005-tilegrid))
$(eval $(call fuzzer,015-clb-nffmux,005-tilegrid))
$(eval $(call fuzzer,016-clb-noutmux,005-tilegrid))
$(eval $(call fuzzer,017-clb-precyinit,005-tilegrid))
$(eval $(call fuzzer,018-clb-ram,005-tilegrid))
$(eval $(call fuzzer,019-clb-ndi1mux,005-tilegrid))
$(eval $(call fuzzer,025-bram-config,005-tilegrid))
$(eval $(call fuzzer,026-bram-data,005-tilegrid))
$(eval $(call fuzzer,050-intpips,005-tilegrid))
$(eval $(call fuzzer,051-imuxlout,050-intpips))
$(eval $(call fuzzer,052-clkin,050-intpips))
$(eval $(call fuzzer,053-ctrlin,050-intpips))
$(eval $(call fuzzer,054-gfan,050-intpips))
$(eval $(call fuzzer,055-gnd,050-intpips))
$(eval $(call fuzzer,056-rempips,051-imuxlout 052-clkin 053-ctrlin 054-gfan 055-gnd))
$(eval $(call fuzzer,057-bipips,056-rempips))
$(eval $(call fuzzer,050-pip-seed,005-tilegrid))
$(eval $(call fuzzer,051-pip-imuxlout,050-pip-seed))
$(eval $(call fuzzer,052-pip-clkin,050-pip-seed))
$(eval $(call fuzzer,053-pip-ctrlin,050-pip-seed))
$(eval $(call fuzzer,054-pip-gfan,050-pip-seed))
$(eval $(call fuzzer,055-pip-gnd,050-pip-seed))
$(eval $(call fuzzer,056-pip-rem,051-pip-imuxlout 052-pip-clkin 053-pip-ctrlin 054-pip-gfan 055-pip-gnd))
$(eval $(call fuzzer,057-pip-bi,056-pip-rem))
ifneq ($(QUICK),Y)
$(eval $(call fuzzer,058-hclkpips,056-rempips))
$(eval $(call fuzzer,071-ppips,057-bipips 058-hclkpips))
$(eval $(call fuzzer,058-pip-hclk,056-pip-rem))
$(eval $(call fuzzer,071-ppips,057-pip-bi 058-pip-hclk))
ifneq ($(BITONLY),Y)
$(eval $(call fuzzer,072-ordered_wires,))
$(eval $(call fuzzer,073-get_counts,))
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