docs: Adding DRAM info to TOC.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
mithro · Apr 4, 2019 · 8c90ae2 · 8c90ae2
1 parent 9717fa4
commit 8c90ae2
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/docs/index.rst b/docs/index.rst
@@ -20,6 +20,7 @@ to develop a free and open Verilog to bitstream toolchain for these devices.
    architecture/overview
    architecture/configuration
    architecture/bitstream_format
+   architecture/dram_configuration
    architecture/glossary
 
 .. toctree::