Merge pull request f4pga#578 from litghost/add_zinv_reg_clk

Add remaining RAMB parameters

fuzzers/025-bram-config/Makefile

@@ -1,6 +1,6 @@
 # read/write width is relatively slow to resolve
 # Even slower with multi bit masks...
-N ?= 8
+N ?= 10
 
 include ../fuzzer.mk
 

fuzzers/025-bram-config/bits.dbf

@@ -3,10 +3,16 @@
 27_43 27_44 27_45,BRAM.RAMB18_Y0.READ_WIDTH_B_1
 27_51 27_52 27_53,BRAM.RAMB18_Y0.WRITE_WIDTH_A_1
 27_59 27_60 27_61,BRAM.RAMB18_Y0.WRITE_WIDTH_B_1
+27_96,BRAM.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE
+27_124,BRAM.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG
+27_125,BRAM.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG
 
 # Y1
 27_285 27_284 27_283,BRAM.RAMB18_Y1.READ_WIDTH_A_1
 27_277 27_276 27_275,BRAM.RAMB18_Y1.READ_WIDTH_B_1
 27_269 27_268 27_267,BRAM.RAMB18_Y1.WRITE_WIDTH_A_1
 27_261 27_260 27_259,BRAM.RAMB18_Y1.WRITE_WIDTH_B_1
+27_224,BRAM.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE
+27_196,BRAM.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG
+27_195,BRAM.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG
 

fuzzers/025-bram-config/generate.py

@@ -1,26 +1,54 @@
 #!/usr/bin/env python3
 
 import json
+import csv
 
 from prjxray.segmaker import Segmaker
 from prjxray import verilog
 from prjxray import segmaker
 
 
-def isinv_tags(segmk, ps, site):
+def isinv_tags(segmk, ps, site, actual_ps):
     # all of these bits are inverted
     ks = [
         ('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
         ('IS_CLKBWRCLK_INVERTED', 'ZINV_CLKBWRCLK'),
+        ('IS_REGCLKARDRCLK_INVERTED', 'ZINV_REGCLKARDRCLK'),
+        ('IS_REGCLKB_INVERTED', 'ZINV_REGCLKB'),
         ('IS_ENARDEN_INVERTED', 'ZINV_ENARDEN'),
         ('IS_ENBWREN_INVERTED', 'ZINV_ENBWREN'),
         ('IS_RSTRAMARSTRAM_INVERTED', 'ZINV_RSTRAMARSTRAM'),
         ('IS_RSTRAMB_INVERTED', 'ZINV_RSTRAMB'),
         ('IS_RSTREGARSTREG_INVERTED', 'ZINV_RSTREGARSTREG'),
         ('IS_RSTREGB_INVERTED', 'ZINV_RSTREGB'),
     ]
+
     for param, tagname in ks:
-        segmk.add_site_tag(site, tagname, 1 ^ verilog.parsei(ps[param]))
+        # The CLK inverts sometimes are changed during synthesis, resulting
+        # in addition inversions.  Take this into account.
+        if param in actual_ps:
+            tag = 1 ^ verilog.parsei(actual_ps[param])
+        elif param == 'IS_REGCLKARDRCLK_INVERTED':
+            if verilog.parsei(ps['DOA_REG']):
+                # When DOA_REG == 1, REGCLKARDRCLK follows the CLKARDCLK setting.
+                tag = 1 ^ verilog.parsei(actual_ps['IS_CLKARDCLK_INVERTED'])
+            else:
+                # When DOA_REG == 0, REGCLKARDRCLK is always inverted.
+                tag = 0
+
+            segmk.add_site_tag(site, tagname, tag)
+        elif param == 'IS_REGCLKB_INVERTED':
+            if verilog.parsei(ps['DOB_REG']):
+                # When DOB_REG == 1, REGCLKB follows the CLKBWRCLK setting.
+                tag = 1 ^ verilog.parsei(actual_ps['IS_CLKBWRCLK_INVERTED'])
+            else:
+                # When DOB_REG == 0, REGCLKB is always inverted.
+                tag = 0
+
+        else:
+            tag = 1 ^ verilog.parsei(ps[param])
+
+        segmk.add_site_tag(site, tagname, tag)
 
 
 def bus_tags(segmk, ps, site):
@@ -72,10 +100,29 @@ def write_mode_tags(segmk, ps, site):
             site, '%s_NO_CHANGE' % (param), set_val == "NO_CHANGE")
 
 
+def write_rstreg_priority(segmk, ps, site):
+    for param in ["RSTREG_PRIORITY_A", "RSTREG_PRIORITY_B"]:
+        set_val = verilog.unquote(ps[param])
+        for opt in ["RSTREG", "REGCE"]:
+            segmk.add_site_tag(
+                site, "{}_{}".format(param, opt), set_val == opt)
+
+
+def write_rdaddr_collision(segmk, ps, site):
+    for opt in ["DELAYED_WRITE", "PERFORMANCE"]:
+        set_val = verilog.unquote(ps['RDADDR_COLLISION_HWCONFIG'])
+        segmk.add_site_tag(
+            site, "RDADDR_COLLISION_HWCONFIG_{}".format(opt), set_val == opt)
+
+
 def run():
 
     segmk = Segmaker("design.bits")
-    #segmk.set_def_bt('BLOCK_RAM')
+
+    clk_inverts = {}
+    with open('design.csv', 'r') as f:
+        for params in csv.DictReader(f):
+            clk_inverts[params['site']] = params
 
     print("Loading tags")
     f = open('params.jl', 'r')
@@ -86,10 +133,12 @@ def run():
         assert j['module'] == 'my_RAMB18E1'
         site = verilog.unquote(ps['LOC'])
 
-        isinv_tags(segmk, ps, site)
+        isinv_tags(segmk, ps, site, clk_inverts[site])
         bus_tags(segmk, ps, site)
         rw_width_tags(segmk, ps, site)
         write_mode_tags(segmk, ps, site)
+        write_rstreg_priority(segmk, ps, site)
+        write_rdaddr_collision(segmk, ps, site)
 
     def bitfilter(frame, bit):
         # rw_width_tags() aliasing interconnect on large widths

fuzzers/025-bram-config/generate.tcl

@@ -23,3 +23,13 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
+
+set fp [open "design.csv" "w"]
+puts $fp "site,IS_CLKARDCLK_INVERTED,IS_CLKBWRCLK_INVERTED"
+foreach ram [get_cells "roi/inst_*/ram"] {
+    set site [get_sites -of_objects [get_bels -of_objects $ram]]
+    set IS_CLKARDCLK_INVERTED [get_property IS_CLKARDCLK_INVERTED $ram]
+    set IS_CLKBWRCLK_INVERTED [get_property IS_CLKBWRCLK_INVERTED $ram]
+    puts $fp "$site,$IS_CLKARDCLK_INVERTED,$IS_CLKBWRCLK_INVERTED"
+}
+close $fp