Merge pull request f4pga#1720 from litghost/update_oserdes_features

Fix remaining known issues with bitstream generation for xc7

xc/common/cmake/vivado.cmake

@@ -112,6 +112,7 @@ function(COMMON_VIVADO_TARGETS)
           --part ${PART}
           --db-root ${PRJRAY_DB_DIR}/${PRJRAY_ARCH}
           --bitread $<TARGET_FILE:bitread>
+          --verbose
           ${CMAKE_CURRENT_BINARY_DIR}/${WORK_DIR}/design_${NAME}.bit
           > ${CMAKE_CURRENT_BINARY_DIR}/${WORK_DIR}/design_${NAME}.bit.fasm
       WORKING_DIRECTORY ${WORK_DIR}
@@ -226,8 +227,10 @@ function(ADD_VIVADO_TARGET)
       append_file_dependency(DEPS ${ADD_VIVADO_TARGET_XDC})
       get_file_location(XDC_LOCATION ${ADD_VIVADO_TARGET_XDC})
       set(XDC_ARGS --additional_xdc "${XDC_LOCATION}")
+      set(CREATE_DCP_ARGS XDC ${ADD_VIVADO_TARGET_XDC})
   elseif()
       set(XDC_ARGS "")
+      set(CREATE_DCP_ARGS "")
   endif()
 
   get_target_property_required(PYTHON3 env PYTHON3)
@@ -281,6 +284,7 @@ function(ADD_VIVADO_TARGET)
         NAME ${NAME}_interchange
         PARENT_NAME ${ADD_VIVADO_TARGET_PARENT_NAME}
         WORK_DIR ${WORK_DIR}/interchange
+        ${CREATE_DCP_ARGS}
         )
   endif()
 
@@ -558,7 +562,7 @@ function(CREATE_DCP_BY_INTERCHANGE)
   #     the bitstream generated from the DCP.
 
   set(options)
-  set(oneValueArgs NAME PARENT_NAME WORK_DIR)
+  set(oneValueArgs NAME PARENT_NAME WORK_DIR XDC)
   set(multiValueArgs)
   cmake_parse_arguments(
       CREATE_DCP
@@ -614,9 +618,17 @@ function(CREATE_DCP_BY_INTERCHANGE)
   set(RUNME_DEPS)
   append_file_dependency(RUNME_DEPS ${WORK_DIR}/${NAME}.dcp)
 
+  set(XDC_EXTRA_ARGS "")
+  if(NOT "${CREATE_DCP_XDC}" STREQUAL "")
+      get_file_location(XDC_LOCATION ${CREATE_DCP_XDC})
+      set(XDC_EXTRA_ARGS "source ${XDC_LOCATION}")
+      append_file_dependency(RUNME_DEPS ${CREATE_DCP_XDC})
+  endif()
+
   add_custom_command(
     OUTPUT ${WORK_DIR}/${NAME}_runme.tcl
     COMMAND ${CMAKE_COMMAND} -E echo "open_checkpoint ${NAME}.dcp"                                     >  ${RUNME}
+    COMMAND ${CMAKE_COMMAND} -E echo "${XDC_EXTRA_ARGS}"                                               >> ${RUNME}
     COMMAND ${CMAKE_COMMAND} -E echo "set_property CFGBVS VCCO [current_design]"                       >> ${RUNME}
     COMMAND ${CMAKE_COMMAND} -E echo "set_property CONFIG_VOLTAGE 3.3 [current_design]"                >> ${RUNME}
     COMMAND ${CMAKE_COMMAND} -E echo "set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]" >> ${RUNME}
@@ -657,6 +669,7 @@ function(CREATE_DCP_BY_INTERCHANGE)
           --part ${PART}
           --db-root ${PRJRAY_DB_DIR}/${PRJRAY_ARCH}
           --bitread $<TARGET_FILE:bitread>
+          --verbose
           ${CMAKE_CURRENT_BINARY_DIR}/${WORK_DIR}/${NAME}.bit
           > ${CMAKE_CURRENT_BINARY_DIR}/${WORK_DIR}/${NAME}.bit.fasm
       WORKING_DIRECTORY ${WORK_DIR}

xc/common/primitives/bram/rambfifo36e1.pb_type.xml

@@ -413,24 +413,33 @@ The RAM has extra bits that can be used for parity (DIP / DOP).
        RAMB18_Y0.DOB_REG = DOB_REG
        RAMB18_Y1.DOB_REG = DOB_REG
 
+       RAMB36.BRAM36_READ_WIDTH_A_1 = BRAM36_READ_WIDTH_A_1
+       RAMB36.BRAM36_READ_WIDTH_B_1 = BRAM36_READ_WIDTH_B_1
+       RAMB36.BRAM36_WRITE_WIDTH_A_1 = BRAM36_WRITE_WIDTH_A_1
+       RAMB36.BRAM36_WRITE_WIDTH_B_1 = BRAM36_WRITE_WIDTH_B_1
+
        RAMB18_Y0.SDP_READ_WIDTH_36 = SDP_READ_WIDTH_36
+
        RAMB18_Y0.READ_WIDTH_A_18 = READ_WIDTH_A_18
        RAMB18_Y0.READ_WIDTH_A_9 = READ_WIDTH_A_9
        RAMB18_Y0.READ_WIDTH_A_4 = READ_WIDTH_A_4
        RAMB18_Y0.READ_WIDTH_A_2 = READ_WIDTH_A_2
        RAMB18_Y0.READ_WIDTH_A_1 = READ_WIDTH_A_1
+
        RAMB18_Y0.READ_WIDTH_B_18 = READ_WIDTH_B_18
        RAMB18_Y0.READ_WIDTH_B_9 = READ_WIDTH_B_9
        RAMB18_Y0.READ_WIDTH_B_4 = READ_WIDTH_B_4
        RAMB18_Y0.READ_WIDTH_B_2 = READ_WIDTH_B_2
        RAMB18_Y0.READ_WIDTH_B_1 = READ_WIDTH_B_1
 
        RAMB18_Y0.SDP_WRITE_WIDTH_36 = SDP_WRITE_WIDTH_36
+
        RAMB18_Y0.WRITE_WIDTH_A_18 = WRITE_WIDTH_A_18
        RAMB18_Y0.WRITE_WIDTH_A_9 = WRITE_WIDTH_A_9
        RAMB18_Y0.WRITE_WIDTH_A_4 = WRITE_WIDTH_A_4
        RAMB18_Y0.WRITE_WIDTH_A_2 = WRITE_WIDTH_A_2
        RAMB18_Y0.WRITE_WIDTH_A_1 = WRITE_WIDTH_A_1
+
        RAMB18_Y0.WRITE_WIDTH_B_18 = WRITE_WIDTH_B_18
        RAMB18_Y0.WRITE_WIDTH_B_9 = WRITE_WIDTH_B_9
        RAMB18_Y0.WRITE_WIDTH_B_4 = WRITE_WIDTH_B_4

xc/common/primitives/ilogice3/ilogice3.pb_type.xml

@@ -362,7 +362,7 @@
 
       <metadata>
         <meta name="fasm_features">
-          IDDR_OR_ISERDES.IN_USE
+          IDDR.IN_USE
         </meta>
         <meta name="fasm_params">
           ZINV_D = ZINV_D

xc/common/primitives/ologice3/ologice3.pb_type.xml

@@ -99,13 +99,13 @@
           <metadata>
             <meta name="fasm_features">
               OSERDES.DATA_RATE_TQ.DDR
+              TDDR.SRUSED
             </meta>
             <meta name="fasm_params">
               ZINV_CLK = ZINV_CLK
               ZINV_T1 = ZINV_D1
               ZINV_T2 = ZINV_D2
               OSERDES.TSRTYPE.SYNC = SRTYPE_SYNC
-              ODDR.DDR_CLK_EDGE.SAME_EDGE = SAME_EDGE
               ZINIT_TQ = ZINIT_Q
               ZSRVAL_TQ = ZSRVAL_Q
             </meta>
@@ -167,6 +167,7 @@
             <meta name="fasm_features">
               OQUSED
               OSERDES.DATA_RATE_OQ.DDR
+              ODDR.SRUSED
             </meta>
             <meta name="fasm_params">
               ZINV_CLK = ZINV_CLK
@@ -296,6 +297,7 @@
           OSERDES.TSRTYPE.SYNC
           ODDR.DDR_CLK_EDGE.SAME_EDGE
           OQUSED
+          ODDR.SRUSED
         </meta>
         <meta name="fasm_params">
           OSERDES.SERDES_MODE.SLAVE = SERDES_MODE_SLAVE
@@ -307,17 +309,19 @@
           OSERDES.DATA_RATE_TQ.BUF = DATA_RATE_TQ_BUF
           OSERDES.DATA_RATE_TQ.DDR = DATA_RATE_TQ_DDR
           OSERDES.DATA_RATE_TQ.SDR = DATA_RATE_TQ_SDR
-
-          OSERDES.DATA_WIDTH.DDR.W6_8 = DATA_WIDTH_DDR_W6_8
-          OSERDES.DATA_WIDTH.SDR.W2_4_5_6 = DATA_WIDTH_SDR_W2_4_5_6
-
-          OSERDES.DATA_WIDTH.W2 = DATA_WIDTH_W2
-          OSERDES.DATA_WIDTH.W3 = DATA_WIDTH_W3
-          OSERDES.DATA_WIDTH.W4 = DATA_WIDTH_W4
-          OSERDES.DATA_WIDTH.W5 = DATA_WIDTH_W5
-          OSERDES.DATA_WIDTH.W6 = DATA_WIDTH_W6
-          OSERDES.DATA_WIDTH.W7 = DATA_WIDTH_W7
-          OSERDES.DATA_WIDTH.W8 = DATA_WIDTH_W8
+          TDDR.SRUSED = TQ_USED
+
+          OSERDES.DATA_WIDTH.SDR.W2 = DATA_WIDTH_SDR_W2
+          OSERDES.DATA_WIDTH.SDR.W3 = DATA_WIDTH_SDR_W3
+          OSERDES.DATA_WIDTH.SDR.W4 = DATA_WIDTH_SDR_W4
+          OSERDES.DATA_WIDTH.SDR.W5 = DATA_WIDTH_SDR_W5
+          OSERDES.DATA_WIDTH.SDR.W6 = DATA_WIDTH_SDR_W6
+          OSERDES.DATA_WIDTH.SDR.W7 = DATA_WIDTH_SDR_W7
+          OSERDES.DATA_WIDTH.SDR.W8 = DATA_WIDTH_SDR_W8
+
+          OSERDES.DATA_WIDTH.DDR.W4 = DATA_WIDTH_DDR_W4
+          OSERDES.DATA_WIDTH.DDR.W6 = DATA_WIDTH_DDR_W6
+          OSERDES.DATA_WIDTH.DDR.W8 = DATA_WIDTH_DDR_W8
 
           ZINIT_OQ = ZINIT_OQ
           ZINIT_TQ = ZINIT_TQ

xc/common/utils/prjxray_routing_import.py

@@ -96,6 +96,75 @@ def reduce_connection_box(box):
     return box
 
 
+class ExtraFeatures():
+    def __init__(self):
+        self.wires_to_nodes = {}
+        self.nodes_to_features = {}
+
+    def extra_features(self, feature_path):
+        if len(feature_path) != 3:
+            return
+
+        key = (feature_path[0], feature_path[1])
+
+        if key in self.wires_to_nodes:
+            return self.nodes_to_features[self.wires_to_nodes[key]]
+
+    def add_feature_to_wire_for_node(self, conn, wire_pkey, feature):
+        cur = conn.cursor()
+
+        cur.execute(
+            """
+SELECT node_pkey FROM wire WHERE pkey = ?;
+            """, (wire_pkey, )
+        )
+        (node_pkey, ) = cur.fetchone()
+
+        if node_pkey not in self.nodes_to_features:
+            self.nodes_to_features[node_pkey] = set()
+
+        self.nodes_to_features[node_pkey].add(feature)
+
+        for (tile_name, wire_name) in cur.execute("""
+SELECT phy_tile.name, wire_in_tile.name
+FROM wire
+INNER JOIN wire_in_tile ON wire.wire_in_tile_pkey = wire_in_tile.pkey
+INNER JOIN phy_tile ON wire.phy_tile_pkey = phy_tile.pkey
+WHERE wire.node_pkey = ?;
+            """, (node_pkey, )):
+            self.wires_to_nodes[tile_name, wire_name] = node_pkey
+
+
+def populate_freq_bb_features(conn, extra_features):
+    cur = conn.cursor()
+
+    cur.execute(
+        """
+SELECT wire.pkey, phy_tile.name, wire_in_tile.name
+FROM wire_in_tile
+INNER JOIN wire ON wire.wire_in_tile_pkey = wire_in_tile.pkey
+INNER JOIN phy_tile ON wire.phy_tile_pkey = phy_tile.pkey
+WHERE wire_in_tile.name LIKE "MMCM_CLK_FREQ_BB_NS%";"""
+    )
+    for wire_pkey, tile_name, wire_name in cur:
+        extra_features.add_feature_to_wire_for_node(
+            conn, wire_pkey, '{}.{}_ACTIVE'.format(tile_name, wire_name)
+        )
+
+    cur.execute(
+        """
+SELECT wire.pkey, phy_tile.name, wire_in_tile.name
+FROM wire_in_tile
+INNER JOIN wire ON wire.wire_in_tile_pkey = wire_in_tile.pkey
+INNER JOIN phy_tile ON wire.phy_tile_pkey = phy_tile.pkey
+WHERE wire_in_tile.name LIKE "PLL_CLK_FREQ_BB%_NS";"""
+    )
+    for wire_pkey, tile_name, wire_name in cur:
+        extra_features.add_feature_to_wire_for_node(
+            conn, wire_pkey, '{}.{}_ACTIVE'.format(tile_name, wire_name)
+        )
+
+
 REBUF_NODES = {}
 REBUF_SOURCES = {}
 
@@ -290,7 +359,7 @@ def find_hclk_cmt_hclk_feature(hclk_tile, lr, hclk_number):
     return ['{}.HCLK_CMT_CK_BUFHCLK{}_USED'.format(hclk_cmt_tile, hclk_number)]
 
 
-def check_feature(feature):
+def check_feature(extra_features, feature):
     """ Check if enabling this feature requires other features to be enabled.
 
     Some pips imply other features.  Example:
@@ -472,6 +541,10 @@ def check_feature(feature):
 
         return ' '.join((feature, enable_cascout))
 
+    extras = extra_features.extra_features(feature_path)
+    if extras is not None:
+        return ' '.join((feature, ) + tuple(extras))
+
     parts = feature.split('.')
 
     wire_feature = feature_when_routed(parts[1])
@@ -1024,7 +1097,7 @@ def get_number_graph_edges(conn, graph, node_mapping):
     return num_edges
 
 
-def import_graph_edges(conn, graph, node_mapping):
+def import_graph_edges(conn, graph, extra_features, node_mapping):
     # First yield existing edges
     print('{} Importing existing edges.'.format(now()))
     for edge in graph.edges:
@@ -1080,7 +1153,7 @@ def import_graph_edges(conn, graph, node_mapping):
             sink_node = node_mapping[dest_graph_node]
 
             if pip_name is not None:
-                feature = check_feature(pip_name)
+                feature = check_feature(extra_features, pip_name)
                 if feature:
                     yield (
                         src_node, sink_node, switch_id,
@@ -1386,6 +1459,8 @@ def main():
     with sqlite3.connect("file:{}?mode=ro".format(args.connection_database),
                          uri=True) as conn:
 
+        extra_features = ExtraFeatures()
+        populate_freq_bb_features(conn, extra_features)
         populate_bufg_rebuf_map(conn)
 
         cur = conn.cursor()
@@ -1472,7 +1547,9 @@ def main():
             num_nodes=len(capnp_graph.graph.nodes),
             nodes_obj=yield_nodes(capnp_graph.graph.nodes),
             num_edges=num_edges,
-            edges_obj=import_graph_edges(conn, graph, node_mapping),
+            edges_obj=import_graph_edges(
+                conn, graph, extra_features, node_mapping
+            ),
             node_remap=node_remap,
         )