Merge pull request f4pga#1466 from antmicro/socs_on_nexys_video

PicoSoC and Murax for Nexys Video
mithro · Jun 29, 2020 · 1daf645 · 1daf645
2 parents 240c535 + aa92041
commit 1daf645
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diff --git a/tests/9-soc/murax/CMakeLists.txt b/tests/9-soc/murax/CMakeLists.txt
@@ -6,11 +6,9 @@ add_file_target(FILE Murax.v_toplevel_system_ram_ram_symbol3.bin)
 add_file_target(FILE hx8k_b_evn_toplevel.v SCANNER_TYPE verilog)
 add_file_target(FILE Murax.v SCANNER_TYPE verilog)
 add_file_target(FILE basys3_toplevel.v SCANNER_TYPE verilog)
-add_file_target(FILE basys3_toplevel_no_roi.v SCANNER_TYPE verilog)
 add_file_target(FILE hx8k-b-evn.pcf)
 add_file_target(FILE basys3.pcf)
 add_file_target(FILE basys3.sdc)
-add_file_target(FILE basys3_full.sdc)
 
 if (NOT DEFINED ENV{CI} OR NOT $ENV{CI})
 add_fpga_target(
@@ -23,8 +21,9 @@ add_fpga_target(
   INPUT_IO_FILE hx8k-b-evn.pcf
   EXPLICIT_ADD_FILE_TARGET
 )
+
 add_fpga_target(
-  NAME murax_basys
+  NAME murax_basys3
   BOARD basys3
   TOP toplevel
   SOURCES
@@ -35,39 +34,100 @@ add_fpga_target(
   EXPLICIT_ADD_FILE_TARGET
 )
 
-add_fpga_target(
-  NAME murax_basys_full
-  BOARD basys3-full
-  TOP toplevel
-  SOURCES
-    basys3_toplevel_no_roi.v
-    Murax.v
-  INPUT_IO_FILE basys3.pcf
-  # TODO: need to fix https://github.com/SymbiFlow/vtr-verilog-to-routing/issues/367
-  #SDC_FILE basys3_full.sdc
-  EXPLICIT_ADD_FILE_TARGET
-)
-
 add_vivado_target(
     NAME murax_basys_vivado
-    PARENT_NAME murax_basys
-    CLOCK_PINS io_mainClk
-    CLOCK_PERIODS 10.0
-    )
-
-add_vivado_target(
-    NAME murax_basys_full_vivado
-    PARENT_NAME murax_basys_full
+    PARENT_NAME murax_basys3
     CLOCK_PINS io_mainClk
     CLOCK_PERIODS 10.0
     )
 
 add_vivado_pnr_target(
     NAME murax_basys_vivado_pnr
-    PARENT_NAME murax_basys
+    PARENT_NAME murax_basys3
     CLOCK_PINS io_mainClk
     CLOCK_PERIODS 10.0
     IOSTANDARD LVCMOS33
     )
+
+# ============================================================================
+# Basys3 (full, no ROI)
+
+add_file_target(FILE basys3-full.pcf)
+
+set(BASYS_FREQS 50 100)
+
+foreach(FREQ ${BASYS_FREQS})
+
+    add_file_target(FILE basys3-full_toplevel_${FREQ}.v SCANNER_TYPE verilog)
+    add_file_target(FILE basys3-full_${FREQ}.sdc)
+
+    add_fpga_target(
+      NAME murax_basys3_full_${FREQ}
+      BOARD basys3-full
+      TOP toplevel
+      SOURCES
+        basys3-full_toplevel_${FREQ}.v
+        Murax.v
+      INPUT_IO_FILE basys3-full.pcf
+      SDC_FILE basys3-full_${FREQ}.sdc
+      EXPLICIT_ADD_FILE_TARGET
+    )
+
+    math(EXPR PERIOD "1000 / ${FREQ}" OUTPUT_FORMAT DECIMAL)
+
+    add_vivado_target(
+        NAME murax_basys3_full_${FREQ}_vivado
+        PARENT_NAME murax_basys3_full_${FREQ}
+        CLOCK_PINS clk
+        CLOCK_PERIODS ${PERIOD}
+        )
+
+endforeach()
+
+# ============================================================================
+# Nexys Video
+
+set(NEXYS_VIDEO_PCF ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/tests/common/nexys_video.pcf)
+set(NEXYS_VIDEO_XDC ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/tests/common/nexys_video.xdc)
+
+get_file_target(TARGET_NEXYS_VIDEO_PCF ${NEXYS_VIDEO_PCF})
+get_file_target(TARGET_NEXYS_VIDEO_XDC ${NEXYS_VIDEO_XDC})
+
+set(NEXYS_VIDEO_FREQS 50 100)
+
+foreach(FREQ ${NEXYS_VIDEO_FREQS})
+
+    add_file_target(FILE nexys_video_toplevel_${FREQ}.v SCANNER_TYPE verilog)
+    add_file_target(FILE nexys_video_${FREQ}.sdc)
+
+    get_file_target(TARGET_NEXYS_VIDEO_DEMO_V nexys_video_toplevel_${FREQ}.v)
+    add_dependencies(${TARGET_NEXYS_VIDEO_DEMO_V} ${TARGET_NEXYS_VIDEO_XDC} ${TARGET_NEXYS_VIDEO_PCF})
+
+    add_fpga_target(
+      NAME murax_nexys_video_${FREQ}
+      BOARD nexys_video
+      TOP top
+      SOURCES
+        nexys_video_toplevel_${FREQ}.v
+        Murax.v
+      SDC_FILE nexys_video_${FREQ}.sdc
+      INPUT_IO_FILE  ${NEXYS_VIDEO_PCF}
+      INPUT_XDC_FILE ${NEXYS_VIDEO_XDC}
+      EXPLICIT_ADD_FILE_TARGET
+    )
+
+    math(EXPR PERIOD "1000 / ${FREQ}" OUTPUT_FORMAT DECIMAL)
+
+    add_vivado_target(
+      NAME murax_nexys_video_${FREQ}_vivado
+      PARENT_NAME murax_nexys_video_${FREQ}
+      CLOCK_PINS clk
+      CLOCK_PERIODS ${PERIOD}
+    )
+
+endforeach()
+
+# ============================================================================
+
 endif (NOT DEFINED ENV{CI} OR NOT $ENV{CI})
 
diff --git a/tests/9-soc/murax/basys3-full.pcf b/tests/9-soc/murax/basys3-full.pcf
@@ -0,0 +1,40 @@
+set_io clk W5
+
+set_io tx A18
+set_io rx B18
+
+# in[0:15] correspond with SW0-SW15 on the basys3
+set_io sw[0] V17
+set_io sw[1] V16
+set_io sw[2] W16
+set_io sw[3] W17
+set_io sw[4] W15
+set_io sw[5] V15
+set_io sw[6] W14
+set_io sw[7] W13
+set_io sw[8] V2
+set_io sw[9] T3
+set_io sw[10] T2
+set_io sw[11] R3
+set_io sw[12] W2
+set_io sw[13] U1
+set_io sw[14] T1
+set_io sw[15] R2
+
+# out[0:15] correspond with LD0-LD15 on the basys3
+set_io io_led[0] U16
+set_io io_led[1] E19
+set_io io_led[2] U19
+set_io io_led[3] V19
+set_io io_led[4] W18
+set_io io_led[5] U15
+set_io io_led[6] U14
+set_io io_led[7] V14
+set_io io_led[8] V13
+set_io io_led[9] V3
+set_io io_led[10] W3
+set_io io_led[11] U3
+set_io io_led[12] P3
+set_io io_led[13] N3
+set_io io_led[14] P1
+set_io io_led[15] L1
diff --git a/tests/9-soc/murax/basys3-full_100.sdc b/tests/9-soc/murax/basys3-full_100.sdc
@@ -0,0 +1 @@
+create_clock -period 10 clk100
diff --git a/tests/9-soc/murax/basys3-full_50.sdc b/tests/9-soc/murax/basys3-full_50.sdc
@@ -0,0 +1,2 @@
+create_clock -period 10 clk100
+create_clock -period 20 clk50
diff --git a/tests/9-soc/murax/basys3_toplevel_no_roi.v → tests/9-soc/murax/basys3-full_toplevel_100.v b/tests/9-soc/murax/basys3_toplevel_no_roi.v → tests/9-soc/murax/basys3-full_toplevel_100.v
@@ -1,15 +1,15 @@
 `timescale 1ns / 1ps
 
 module toplevel(
-    input   io_mainClk,
-    output  io_uart_txd,
-    input   io_uart_rxd,
+    input   clk,
+    output  tx,
+    input   rx,
     input [15:0] sw,
     output [15:0] io_led
   );
 
-  wire io_mainClk_bufg;
-  BUFG bufg(.I(io_mainClk), .O(io_mainClk_bufg));
+  wire clk100;
+  BUFG bufg(.I(clk), .O(clk100));
 
   wire [31:0] io_gpioA_read;
   wire [31:0] io_gpioA_write;
@@ -27,14 +27,14 @@ module toplevel(
 
   Murax murax (
     .io_asyncReset(0),
-    .io_mainClk (io_mainClk_bufg ),
+    .io_mainClk (clk100),
     .io_jtag_tck(1'b0),
     .io_jtag_tdi(1'b0),
     .io_jtag_tms(1'b0),
     .io_gpioA_read       (io_gpioA_read),
     .io_gpioA_write      (io_gpioA_write),
     .io_gpioA_writeEnable(io_gpioA_writeEnable),
-    .io_uart_txd(io_uart_txd),
-    .io_uart_rxd(io_uart_rxd)
+    .io_uart_txd(tx),
+    .io_uart_rxd(rx)
   );
 endmodule
diff --git a/tests/9-soc/murax/basys3-full_toplevel_50.v b/tests/9-soc/murax/basys3-full_toplevel_50.v
@@ -0,0 +1,48 @@
+`timescale 1ns / 1ps
+
+module toplevel(
+    input   clk,
+    output  tx,
+    input   rx,
+    input [15:0] sw,
+    output [15:0] io_led
+  );
+
+  wire clk100;
+  BUFG bufg(.I(clk), .O(clk100));
+
+  // BUFGCE as divide by 2
+  reg clk50_ce;
+  always @(posedge clk100)
+      clk50_ce <= !clk50_ce;
+
+  wire clk50;
+  BUFGCE bufg50 (.I(clk), .CE(clk50_ce), .O(clk50));
+
+  wire [31:0] io_gpioA_read;
+  wire [31:0] io_gpioA_write;
+  wire [31:0] io_gpioA_writeEnable;
+  wire io_mainClk;
+  wire io_jtag_tck;
+  wire io_jtag_tdi;
+  wire io_jtag_tdo;
+  wire io_jtag_tms;
+  wire io_uart_txd;
+  wire io_uart_rxd;
+
+  assign io_led = io_gpioA_write[15: 0];
+  assign io_gpioA_read[15:0] = sw;
+
+  Murax murax (
+    .io_asyncReset(0),
+    .io_mainClk (clk50),
+    .io_jtag_tck(1'b0),
+    .io_jtag_tdi(1'b0),
+    .io_jtag_tms(1'b0),
+    .io_gpioA_read       (io_gpioA_read),
+    .io_gpioA_write      (io_gpioA_write),
+    .io_gpioA_writeEnable(io_gpioA_writeEnable),
+    .io_uart_txd(tx),
+    .io_uart_rxd(rx)
+  );
+endmodule
diff --git a/tests/9-soc/murax/basys3_full.sdc b/tests/9-soc/murax/basys3_full.sdc
diff --git a/tests/9-soc/murax/nexys_video_100.sdc b/tests/9-soc/murax/nexys_video_100.sdc
@@ -0,0 +1 @@
+create_clock -period 10 clk100
diff --git a/tests/9-soc/murax/nexys_video_50.sdc b/tests/9-soc/murax/nexys_video_50.sdc
@@ -0,0 +1,2 @@
+create_clock -period 10 clk100
+create_clock -period 20 clk50
diff --git a/tests/9-soc/murax/nexys_video_toplevel_100.v b/tests/9-soc/murax/nexys_video_toplevel_100.v
@@ -0,0 +1,40 @@
+`timescale 1ns / 1ps
+
+module top (
+    input  clk,
+    output tx,
+    input  rx,
+    input  [7:0] sw,
+    output [7:0] led
+  );
+
+  wire [31:0] io_gpioA_read;
+  wire [31:0] io_gpioA_write;
+  wire [31:0] io_gpioA_writeEnable;
+  wire io_mainClk;
+  wire io_jtag_tck;
+  wire io_jtag_tdi;
+  wire io_jtag_tdo;
+  wire io_jtag_tms;
+  wire io_uart_txd;
+  wire io_uart_rxd;
+
+  assign led = io_gpioA_write[7: 0];
+  assign io_gpioA_read[7:0] = sw;
+
+  wire clk_bufg;
+  BUFG bufg (.I(clk), .O(clk100));
+
+  Murax murax (
+    .io_asyncReset(0),
+    .io_mainClk (clk100),
+    .io_jtag_tck(1'b0),
+    .io_jtag_tdi(1'b0),
+    .io_jtag_tms(1'b0),
+    .io_gpioA_read       (io_gpioA_read),
+    .io_gpioA_write      (io_gpioA_write),
+    .io_gpioA_writeEnable(io_gpioA_writeEnable),
+    .io_uart_txd(tx),
+    .io_uart_rxd(rx)
+  );
+endmodule
diff --git a/tests/9-soc/murax/nexys_video_toplevel_50.v b/tests/9-soc/murax/nexys_video_toplevel_50.v
@@ -0,0 +1,48 @@
+`timescale 1ns / 1ps
+
+module top (
+    input  clk,
+    output tx,
+    input  rx,
+    input  [7:0] sw,
+    output [7:0] led
+  );
+
+  wire [31:0] io_gpioA_read;
+  wire [31:0] io_gpioA_write;
+  wire [31:0] io_gpioA_writeEnable;
+  wire io_mainClk;
+  wire io_jtag_tck;
+  wire io_jtag_tdi;
+  wire io_jtag_tdo;
+  wire io_jtag_tms;
+  wire io_uart_txd;
+  wire io_uart_rxd;
+
+  assign led = io_gpioA_write[7: 0];
+  assign io_gpioA_read[7:0] = sw;
+
+  wire clk_bufg;
+  BUFG bufg (.I(clk), .O(clk100));
+
+  // BUFGCE as divide by 2
+  reg clk50_ce;
+  always @(posedge clk100)
+      clk50_ce <= !clk50_ce;
+
+  wire clk50;
+  BUFGCE bufg50 (.I(clk), .CE(clk50_ce), .O(clk50));
+
+  Murax murax (
+    .io_asyncReset(0),
+    .io_mainClk (clk50),
+    .io_jtag_tck(1'b0),
+    .io_jtag_tdi(1'b0),
+    .io_jtag_tms(1'b0),
+    .io_gpioA_read       (io_gpioA_read),
+    .io_gpioA_write      (io_gpioA_write),
+    .io_gpioA_writeEnable(io_gpioA_writeEnable),
+    .io_uart_txd(tx),
+    .io_uart_rxd(rx)
+  );
+endmodule