Merge pull request f4pga#2238 from antmicro/pp3-const-port-names

[PP3] Update Yosys plugins
mithro · Aug 4, 2021 · 25cc29b · 25cc29b
2 parents 958839c + 864cb87
commit 25cc29b
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Showing 2 changed files with 5 additions and 5 deletions.
diff --git a/environment.yml b/environment.yml
@@ -9,7 +9,7 @@ dependencies:
   - litex-hub::icestorm=0.0_0719_g792cef0=20201120_145821
   - litex-hub::iverilog=s20150603_0957_gad862020=20201120_145821
   - litex-hub::openocd=0.10.0_1514_ga8edbd020=20201119_154304
-  - litex-hub::symbiflow-yosys-plugins=1.0.0_7_366_g5d91d44=20210625_074838
+  - litex-hub::symbiflow-yosys-plugins=1.0.0_7_368_gfc33276=20210730_085634
   - litex-hub::prjxray-tools=0.1_2842_g6867429c=20210301_104249
   - litex-hub::prjxray-db=0.0_248_g2e51ad3=20210312_125539
   - litex-hub::vtr-optimized=8.0.0_3614_gb3b34e77a=20210507_125510

diff --git a/quicklogic/pp3/techmap/cells_map.v b/quicklogic/pp3/techmap/cells_map.v
@@ -3,12 +3,12 @@
 
 // Reduce logic_0 and logic_1 cells to 1'b0 and 1'b1. Const sources suitable
 // for VPR will be added by Yosys during EBLIF write.
-module logic_0(output A);
-    assign A = 0;
+module logic_0(output a);
+    assign a = 0;
 endmodule
 
-module logic_1(output A);
-    assign A = 1;
+module logic_1(output a);
+    assign a = 1;
 endmodule