Skip to content

Commit

Permalink
Merge pull request f4pga#861 from antmicro/bram-timings
Browse files Browse the repository at this point in the history 
Imported bram timings
  • Loading branch information
@acomodi
acomodi committed Jul 1, 2019
2 parents 86ce940 + b502907 commit 31732ac
Show file tree
Hide file tree
Showing 3 changed files with 122 additions and 56 deletions.
14 changes: 14 additions & 0 deletions xc7/bels.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -284,5 +284,19 @@
"instance": "SLICEM"
}
}
},
"BRAM_X" : {
"RAMB36E1":{
"RAMBFIFO36E1":{
"celltype": "RAMBFIFO36E1 RAMBFIFO36E1_DOA_REG_U_1 RAMBFIFO36E1_DOB_REG_U_1 RAMBFIFO36E1_ISFIFO_FALSE RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_RF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOA_REG_U_1_EN_ECC_READ_FALSE RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOB_REG_U_1_EN_ECC_READ_FALSE",
"instance": "RAMBFIFO36E1"
}
},
"RAMB18E1":{
"BRAM":{
"celltype": "RAMBFIFO36E1 RAMBFIFO36E1_DOA_REG_U_1 RAMBFIFO36E1_DOB_REG_U_1 RAMBFIFO36E1_ISFIFO_FALSE RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_RF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOA_REG_U_1_EN_ECC_READ_FALSE RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOB_REG_U_1_EN_ECC_READ_FALSE",
"instance": "RAMBFIFO36E1"
}
}
}
}
64 changes: 42 additions & 22 deletions xc7/primitives/bram/ramb18e1.pb_type.xml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,17 +24,27 @@ The RAM has extra bits that can be used for parity (DIP / DOP).
<output name="DOADO" num_pins="16" />
<output name="DOPADOP" num_pins="2" />

<T_setup value="10e-12" port="REGCEAREGCE" clock="CLKARDCLK" />
<T_setup value="10e-12" port="REGCLKARDRCLK" clock="CLKARDCLK" />
<T_setup value="10e-12" port="ENARDEN" clock="CLKARDCLK" />
<T_setup value="10e-12" port="RSTRAMARSTRAM" clock="CLKARDCLK" />
<T_setup value="10e-12" port="RSTREGARSTREG" clock="CLKARDCLK" />
<T_setup value="10e-12" port="ADDRARDADDR" clock="CLKARDCLK" />
<T_setup value="10e-12" port="DIADI" clock="CLKARDCLK" />
<T_setup value="10e-12" port="DIPADIP" clock="CLKARDCLK" />
<T_setup value="10e-12" port="WEA" clock="CLKARDCLK" />
<T_clock_to_Q max="10e-12" port="DOADO" clock="CLKARDCLK" />
<T_clock_to_Q max="10e-12" port="DOPADOP" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_ENARDENU}" port="ENARDEN" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_ENARDENU}" port="ENARDEN" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKL_REGCEAL}" port="REGCEAREGCE" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKL_REGCEAL}" port="REGCEAREGCE" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAM" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAM" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREG" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREG" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_ADDRAU}" port="ADDRARDADDR" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_ADDRAU}" port="ADDRARDADDR" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_DIADIU}" port="DIADI" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_DIADIU}" port="DIADI" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_DIPADIPU}" port="DIPADIP" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_DIPADIPU}" port="DIPADIP" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_WEAU}" port="WEA" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_WEAU}" port="WEA" clock="CLKARDCLK" />
<T_clock_to_Q max="{iopath_CLKARDCLKU_DOADOU}" port="DOADO" clock="CLKARDCLK" />
<T_clock_to_Q max="{iopath_CLKARDCLKU_DOPADOPU}" port="DOPADOP" clock="CLKARDCLK" />

<!-- Fake timing values as there is no database entry for these i/o -->
<T_setup value="10e-12" port="REGCLKARDRCLK" clock="CLKARDCLK" />

<!-- Port B - 16bit wide -->
<clock name="CLKBWRCLK" num_pins="1" />
Expand All @@ -51,17 +61,27 @@ The RAM has extra bits that can be used for parity (DIP / DOP).
<output name="DOBDO" num_pins="16" />
<output name="DOPBDOP" num_pins="2" />

<T_setup value="10e-12" port="ENBWREN" clock="CLKBWRCLK" />
<T_setup value="10e-12" port="REGCEB" clock="CLKBWRCLK" />
<T_setup value="10e-12" port="REGCLKB" clock="CLKBWRCLK" />
<T_setup value="10e-12" port="RSTRAMB" clock="CLKBWRCLK" />
<T_setup value="10e-12" port="RSTREGB" clock="CLKBWRCLK" />
<T_setup value="10e-12" port="ADDRBWRADDR" clock="CLKBWRCLK" />
<T_setup value="10e-12" port="DIBDI" clock="CLKBWRCLK" />
<T_setup value="10e-12" port="DIPBDIP" clock="CLKBWRCLK" />
<T_setup value="10e-12" port="WEBWE" clock="CLKBWRCLK" />
<T_clock_to_Q max="10e-12" port="DOBDO" clock="CLKBWRCLK" />
<T_clock_to_Q max="10e-12" port="DOPBDOP" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_ENBWRENU}" port="ENBWREN" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_ENBWRENU}" port="ENBWREN" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_REGCEBU}" port="REGCEB" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_REGCEBU}" port="REGCEB" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMB" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMB" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_RSTREGBU}" port="RSTREGB" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_RSTREGBU}" port="RSTREGB" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_ADDRBU}" port="ADDRBWRADDR" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_ADDRBU}" port="ADDRBWRADDR" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_DIBDIU}" port="DIBDI" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_DIBDIU}" port="DIBDI" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_DIPBDIPU}" port="DIPBDIP" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_DIPBDIPU}" port="DIPBDIP" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_WEBU}" port="WEBWE" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_WEBU}" port="WEBWE" clock="CLKBWRCLK" />
<T_clock_to_Q max="{iopath_CLKBWRCLKU_DOBDOU}" port="DOBDO" clock="CLKBWRCLK" />
<T_clock_to_Q max="{iopath_CLKBWRCLKU_DOPBDOPU}" port="DOPBDOP" clock="CLKBWRCLK" />

<!-- Fake timing values as there is no database entry for these i/o -->
<T_setup value="10e-12" port="REGCLKB" clock="CLKBWRCLK" />

<metadata>
<meta name="fasm_params">
Expand Down
100 changes: 66 additions & 34 deletions xc7/primitives/bram/rambfifo36e1.pb_type.xml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -122,24 +122,40 @@ The RAM has extra bits that can be used for parity (DIP / DOP).
<output name="DOADO" num_pins="32" />
<output name="DOPADOP" num_pins="4" />

<T_setup value="10e-12" port="REGCEAREGCEU" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="REGCEAREGCEL" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKL_REGCEAL}" port="REGCEAREGCEU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKL_REGCEAL}" port="REGCEAREGCEU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKL_REGCEAL}" port="REGCEAREGCEL" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKL_REGCEAL}" port="REGCEAREGCEL" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_ENARDENU}" port="ENARDENU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_ENARDENU}" port="ENARDENU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_ENARDENU}" port="ENARDENL" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_ENARDENU}" port="ENARDENL" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAMU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAMU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAMLRST" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAMLRST" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREGU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREGU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREGL" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREGL" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_ADDRAU}" port="ADDRARDADDRU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_ADDRAU}" port="ADDRARDADDRU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_ADDRA15L}" port="ADDRARDADDRL" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_ADDRA15L}" port="ADDRARDADDRL" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_DIADIU}" port="DIADI" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_DIADIU}" port="DIADI" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_DIPADIPU}" port="DIPADIP" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_DIPADIPU}" port="DIPADIP" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_WEAU}" port="WEAU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_WEAU}" port="WEAU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_WEAU}" port="WEAL" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_WEAU}" port="WEAL" clock="CLKARDCLKL" />
<T_clock_to_Q max="{iopath_CLKARDCLKU_DOADOU}" port="DOADO" clock="CLKARDCLKL" />
<T_clock_to_Q max="{iopath_CLKARDCLKU_DOPADOPU}" port="DOPADOP" clock="CLKARDCLKL" />

<!-- Fake timing values as there is no database entry for these i/o -->
<T_setup value="10e-12" port="REGCLKARDRCLKU" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="REGCLKARDRCLKL" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="ENARDENU" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="ENARDENL" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="RSTRAMARSTRAMU" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="RSTRAMARSTRAMLRST" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="RSTREGARSTREGU" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="RSTREGARSTREGL" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="ADDRARDADDRU" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="ADDRARDADDRL" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="DIADI" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="DIPADIP" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="WEAU" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="WEAL" clock="CLKARDCLKL" />
<T_clock_to_Q max="10e-12" port="DOADO" clock="CLKARDCLKL" />
<T_clock_to_Q max="10e-12" port="DOPADOP" clock="CLKARDCLKL" />

<!-- Port B - 32bit wide -->
<clock name="CLKBWRCLKU" num_pins="1" />
Expand All @@ -163,24 +179,40 @@ The RAM has extra bits that can be used for parity (DIP / DOP).
<output name="DOBDO" num_pins="32" />
<output name="DOPBDOP" num_pins="4" />

<T_setup value="10e-12" port="ENBWRENU" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="ENBWRENL" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="REGCEBU" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="REGCEBL" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="REGCLKBU" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="REGCLKBL" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="RSTRAMBU" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="RSTRAMBL" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="RSTREGBU" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="RSTREGBL" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="ADDRBWRADDRU" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="ADDRBWRADDRL" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="DIBDI" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="DIPBDIP" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="WEBWEU" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="WEBWEL" clock="CLKBWRCLKL" />
<T_clock_to_Q max="10e-12" port="DOBDO" clock="CLKBWRCLKL" />
<T_clock_to_Q max="10e-12" port="DOPBDOP" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_ENBWRENU}" port="ENBWRENU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_ENBWRENU}" port="ENBWRENU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_ENBWRENU}" port="ENBWRENL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_ENBWRENU}" port="ENBWRENL" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_REGCEBU}" port="REGCEBU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_REGCEBU}" port="REGCEBU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_REGCEBU}" port="REGCEBL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_REGCEBU}" port="REGCEBL" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMBU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMBU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMBL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMBL" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_RSTREGBU}" port="RSTREGBU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_RSTREGBU}" port="RSTREGBU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_RSTREGBU}" port="RSTREGBL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_RSTREGBU}" port="RSTREGBL" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_ADDRBU}" port="ADDRBWRADDRU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_ADDRBU}" port="ADDRBWRADDRU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_ADDRB15L}" port="ADDRBWRADDRL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_ADDRB15L}" port="ADDRBWRADDRL" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_DIBDIU}" port="DIBDI" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_DIBDIU}" port="DIBDI" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_DIPBDIPU}" port="DIPBDIP" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_DIPBDIPU}" port="DIPBDIP" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_WEBU}" port="WEBWEU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_WEBU}" port="WEBWEU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_WEBU}" port="WEBWEL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_WEBU}" port="WEBWEL" clock="CLKBWRCLKL" />
<T_clock_to_Q max="{iopath_CLKBWRCLKU_DOBDOU}" port="DOBDO" clock="CLKBWRCLKL" />
<T_clock_to_Q max="{iopath_CLKBWRCLKU_DOPBDOPU}" port="DOPBDOP" clock="CLKBWRCLKL" />

<!-- Fake timing values as there is no database entry for these i/o -->
<T_setup value="10e-12" port="REGCLKBU" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="REGCLKBL" clock="CLKBWRCLKL" />

<input name="CASCADEINA" num_pins="1" />
<input name="CASCADEINB" num_pins="1" />
Expand Down

0 comments on commit 31732ac

Please sign in to comment.