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Merge pull request #77 from daveshah1/v2xml-work
Improvements to XML from Verilog Generation
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artix7/primitives/slicel/carry4/carry4_complete/carry4/carry4.model.xml
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artix7/primitives/slicel/carry4/carry4_complete/carry4/carry4.pb_type.xml
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artix7/primitives/slicel/carry4/carry4_complete/carry4_complete.model.xml
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artix7/primitives/slicel/carry4/carry4_complete/carry4_complete.pb_type.xml
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artix7/primitives/slicel/carry4/carry4_complete/carry4_complete.sim.v
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artix7/primitives/slicel/carry4/carry4_split/carry4_split.model.xml
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artix7/primitives/slicel/carry4/carry4_split/carry4_split.pb_type.xml
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`include "carry4/carry4.sim.v" | ||
`include "carry4_split/carry4_split.sim.v" | ||
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(* MODES = "SPLIT; COMPLETE" *) | ||
module CARRY4_MODES(CO, O, CIN, DI, S); | ||
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output wire [3:0] CO; | ||
output wire [3:0] O; | ||
input CIN; | ||
input [3:0] DI; | ||
input [3:0] S; | ||
parameter MODE = "SPLIT"; | ||
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generate | ||
if (MODE == "SPLIT") begin | ||
CARRY4_SPLIT split_i(.CO(CO), .O(O), .CIN(CIN), .DI(DI), .S(S)); | ||
end else if (MODE == "COMPLETE") begin | ||
CARRY4 complete_i(.CO(CO), .O(O), .CIN(CIN), .DI(DI), .S(S)); | ||
end | ||
endgenerate | ||
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endmodule |
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