Merge pull request f4pga#1640 from antmicro/params_plugin_integration

xc7: yosys: Use params plugin to update PLL's PHASE params
mithro · Sep 10, 2020 · 552d428 · 552d428
2 parents b3864ae + 9d0739e
commit 552d428
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Showing 16 changed files with 47 additions and 12 deletions.
diff --git a/environment.yml b/environment.yml
@@ -4,7 +4,7 @@ channels:
   - symbiflow
 dependencies:
   - symbiflow-yosys=0.8_6021_gd8b2d1a2=20200708_083630
-  - symbiflow-yosys-plugins=1.0.0.7_0048_gaa1b583=20200706_223638
+  - symbiflow-yosys-plugins=1.0.0.7_0060_g7454cd6=20200902_114536
   - symbiflow-vtr=8.0.0.rc2_4003_g8980e4621=20200720_145630
   - cmake
   - make

diff --git a/xc/common/cmake/arch_define.cmake b/xc/common/cmake/arch_define.cmake
@@ -11,6 +11,7 @@ function(ADD_XC_ARCH_DEFINE)
   #   PROTOTYPE_PART <prototype_part>
   #   YOSYS_SYNTH_SCRIPT <yosys_script>
   #   YOSYS_CONV_SCRIPT <yosys_script>
+  #   YOSYS_UTILS_SCRIPT <yosys_script>
   #   )
   #
   # FAMILY: The family the architecture is belonging to (e.g. xc7).
@@ -30,7 +31,8 @@ function(ADD_XC_ARCH_DEFINE)
         PRJRAY_NAME
         PROTOTYPE_PART
         YOSYS_SYNTH_SCRIPT
-        YOSYS_CONV_SCRIPT)
+        YOSYS_CONV_SCRIPT
+        YOSYS_UTILS_SCRIPT)
   set(multiValueArgs)
   cmake_parse_arguments(
     ADD_XC_ARCH_DEFINE
@@ -57,6 +59,7 @@ function(ADD_XC_ARCH_DEFINE)
   set(PROTOTYPE_PART ${ADD_XC_ARCH_DEFINE_PROTOTYPE_PART})
   set(YOSYS_SYNTH_SCRIPT ${ADD_XC_ARCH_DEFINE_YOSYS_SYNTH_SCRIPT})
   set(YOSYS_CONV_SCRIPT ${ADD_XC_ARCH_DEFINE_YOSYS_CONV_SCRIPT})
+  set(YOSYS_UTILS_SCRIPT ${ADD_XC_ARCH_DEFINE_YOSYS_UTILS_SCRIPT})
   set(YOSYS_TECHMAP ${symbiflow-arch-defs_SOURCE_DIR}/xc/${FAMILY}/techmap)
   set(VPR_ARCH_ARGS "\
       --router_heap bucket \
@@ -181,6 +184,7 @@ function(ADD_XC_ARCH_DEFINE)
       ROUTE_CHAN_WIDTH 500
       VPR_ARCH_ARGS ${VPR_ARCH_ARGS}
       CONV_SCRIPT ${YOSYS_CONV_SCRIPT}
-      SYNTH_SCRIPT ${YOSYS_SYNTH_SCRIPT})
+      SYNTH_SCRIPT ${YOSYS_SYNTH_SCRIPT}
+      UTILS_SCRIPT ${YOSYS_UTILS_SCRIPT})
 
 endfunction()
diff --git a/xc/common/cmake/install.cmake b/xc/common/cmake/install.cmake
@@ -1,6 +1,6 @@
 function(DEFINE_XC_TOOLCHAIN_TARGET)
   set(options)
-  set(oneValueArgs ARCH CONV_SCRIPT SYNTH_SCRIPT ROUTE_CHAN_WIDTH)
+  set(oneValueArgs ARCH CONV_SCRIPT SYNTH_SCRIPT UTILS_SCRIPT ROUTE_CHAN_WIDTH)
   set(multiValueArgs VPR_ARCH_ARGS)
 
   cmake_parse_arguments(
@@ -81,7 +81,7 @@ function(DEFINE_XC_TOOLCHAIN_TARGET)
           DESTINATION share/symbiflow/techmaps/${FAMILY}_vpr)
 
   # install Yosys scripts
-  install(FILES  ${DEFINE_XC_TOOLCHAIN_TARGET_CONV_SCRIPT} ${DEFINE_XC_TOOLCHAIN_TARGET_SYNTH_SCRIPT}
+  install(FILES  ${DEFINE_XC_TOOLCHAIN_TARGET_CONV_SCRIPT} ${DEFINE_XC_TOOLCHAIN_TARGET_SYNTH_SCRIPT} ${DEFINE_XC_TOOLCHAIN_TARGET_UTILS_SCRIPT}
     DESTINATION share/symbiflow/scripts/${FAMILY})
 
 endfunction()

diff --git a/xc/xc7/archs/artix7/CMakeLists.txt b/xc/xc7/archs/artix7/CMakeLists.txt
@@ -15,6 +15,7 @@ add_xc_arch_define(
   PROTOTYPE_PART xc7a50tfgg484-1
   YOSYS_SYNTH_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/synth.tcl
   YOSYS_CONV_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/conv.tcl
+  YOSYS_UTILS_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/utils.tcl
 )
 
 add_subdirectory(tiles)

diff --git a/xc/xc7/archs/artix7_100t/CMakeLists.txt b/xc/xc7/archs/artix7_100t/CMakeLists.txt
@@ -16,6 +16,7 @@ add_xc_arch_define(
   PROTOTYPE_PART xc7a100tfgg676-1
   YOSYS_SYNTH_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/synth.tcl
   YOSYS_CONV_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/conv.tcl
+  YOSYS_UTILS_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/utils.tcl
 )
 
 add_subdirectory(tiles)

diff --git a/xc/xc7/archs/artix7_200t/CMakeLists.txt b/xc/xc7/archs/artix7_200t/CMakeLists.txt
@@ -16,6 +16,7 @@ add_xc_arch_define(
   PROTOTYPE_PART xc7a200tffg1156-1
   YOSYS_SYNTH_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/synth.tcl
   YOSYS_CONV_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/conv.tcl
+  YOSYS_UTILS_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/utils.tcl
 )
 
 add_subdirectory(tiles)

diff --git a/xc/xc7/archs/zynq7/CMakeLists.txt b/xc/xc7/archs/zynq7/CMakeLists.txt
@@ -15,6 +15,7 @@ add_xc_arch_define(
   PROTOTYPE_PART xc7z010clg400-1
   YOSYS_SYNTH_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/synth.tcl
   YOSYS_CONV_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/conv.tcl
+  YOSYS_UTILS_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/utils.tcl
 )
 
 add_subdirectory(tiles)

diff --git a/xc/xc7/archs/zynq7_z020/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/CMakeLists.txt
@@ -2,7 +2,7 @@ project_ray_prepare_database(
   PRJRAY_ARCH zynq7
   PRJRAY_DIR ${PRJXRAY_DIR}
   PRJRAY_DB_DIR ${PRJXRAY_DB_DIR}
-  PROTOTYPE_PART xc7z020clg484-1  
+  PROTOTYPE_PART xc7z020clg484-1
   PARTS xc7z020clg484-1
 )
 
@@ -16,6 +16,7 @@ add_xc_arch_define(
   PROTOTYPE_PART xc7z020clg484-1
   YOSYS_SYNTH_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/synth.tcl
   YOSYS_CONV_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/conv.tcl
+  YOSYS_UTILS_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/utils.tcl
 )
 
 add_subdirectory(tiles)

diff --git a/xc/xc7/tests/ddr/ddr_uart.v b/xc/xc7/tests/ddr/ddr_uart.v
@@ -11757,7 +11757,7 @@ PLLE2_ADV #(
 	.CLKOUT1_DIVIDE(4'd8),
 	.CLKOUT1_PHASE(1'd0),
 	.CLKOUT2_DIVIDE(4'd8),
-	.CLKOUT2_PHASE(90000),
+	.CLKOUT2_PHASE(7'd90),
 	.CLKOUT3_DIVIDE(4'd8),
 	.CLKOUT3_PHASE(1'd0),
 	.DIVCLK_DIVIDE(1'd1),

diff --git a/xc/xc7/tests/ddr/ddr_uart_100t.v b/xc/xc7/tests/ddr/ddr_uart_100t.v
@@ -11758,7 +11758,7 @@ PLLE2_ADV #(
 	.CLKOUT1_DIVIDE(4'd8),
 	.CLKOUT1_PHASE(1'd0),
 	.CLKOUT2_DIVIDE(4'd8),
-	.CLKOUT2_PHASE(90000),
+	.CLKOUT2_PHASE(7'd90),
 	.CLKOUT3_DIVIDE(4'd8),
 	.CLKOUT3_PHASE(1'd0),
 	.DIVCLK_DIVIDE(1'd1),

diff --git a/xc/xc7/tests/soc/litex/base/baselitex_arty.v b/xc/xc7/tests/soc/litex/base/baselitex_arty.v
@@ -13398,7 +13398,7 @@ PLLE2_ADV #(
 	.CLKOUT1_DIVIDE(3'd5),
 	.CLKOUT1_PHASE(1'd0),
 	.CLKOUT2_DIVIDE(3'd5),
-	.CLKOUT2_PHASE(90000),
+	.CLKOUT2_PHASE(7'd90),
 	.CLKOUT3_DIVIDE(3'd6),
 	.CLKOUT3_PHASE(1'd0),
 	.CLKOUT4_DIVIDE(6'd48),

diff --git a/xc/xc7/tests/soc/litex/base/baselitex_arty100t.v b/xc/xc7/tests/soc/litex/base/baselitex_arty100t.v
@@ -13399,7 +13399,7 @@ PLLE2_ADV #(
 	.CLKOUT1_DIVIDE(3'd5),
 	.CLKOUT1_PHASE(1'd0),
 	.CLKOUT2_DIVIDE(3'd5),
-	.CLKOUT2_PHASE(90000),
+	.CLKOUT2_PHASE(7'd90),
 	.CLKOUT3_DIVIDE(3'd6),
 	.CLKOUT3_PHASE(1'd0),
 	.CLKOUT4_DIVIDE(6'd48),

diff --git a/xc/xc7/tests/soc/litex/mini_ddr/minilitex_ddr_arty.v b/xc/xc7/tests/soc/litex/mini_ddr/minilitex_ddr_arty.v
@@ -12203,7 +12203,7 @@ PLLE2_ADV #(
 	.CLKOUT1_DIVIDE(3'd5),
 	.CLKOUT1_PHASE(1'd0),
 	.CLKOUT2_DIVIDE(3'd5),
-	.CLKOUT2_PHASE(90000),
+	.CLKOUT2_PHASE(7'd90),
 	.CLKOUT3_DIVIDE(3'd6),
 	.CLKOUT3_PHASE(1'd0),
 	.DIVCLK_DIVIDE(1'd1),

diff --git a/xc/xc7/tests/soc/litex/mini_ddr/minilitex_ddr_arty100t.v b/xc/xc7/tests/soc/litex/mini_ddr/minilitex_ddr_arty100t.v
@@ -12204,7 +12204,7 @@ PLLE2_ADV #(
 	.CLKOUT1_DIVIDE(3'd5),
 	.CLKOUT1_PHASE(1'd0),
 	.CLKOUT2_DIVIDE(3'd5),
-	.CLKOUT2_PHASE(90000),
+	.CLKOUT2_PHASE(7'd90),
 	.CLKOUT3_DIVIDE(3'd6),
 	.CLKOUT3_PHASE(1'd0),
 	.DIVCLK_DIVIDE(1'd1),

diff --git a/xc/xc7/yosys/synth.tcl b/xc/xc7/yosys/synth.tcl
@@ -2,10 +2,14 @@ yosys -import
 
 plugin -i xdc
 plugin -i fasm
+plugin -i params
+plugin -i selection
 
 # Import the commands from the plugins to the tcl interpreter
 yosys -import
 
+source [file join [file normalize [info script]] .. utils.tcl]
+
 # -flatten is used to ensure that the output eblif has only one module.
 # Some of symbiflow expects eblifs with only one module.
 #
@@ -21,6 +25,7 @@ if { $::env(USE_ROI) == "TRUE" } {
     read_verilog -lib $::env(TECHMAP_PATH)/iobs.v
 
     hierarchy -check -auto-top
+    update_pll_params
 
     # Start flow after library reading
     synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -nowidelut -run prepare:check

diff --git a/xc/xc7/yosys/utils.tcl b/xc/xc7/yosys/utils.tcl
@@ -0,0 +1,21 @@
+# Update the CLKOUT[0-5]_PHASE and CLKOUT[0-5]_DUTY_CYCLE parameter values.
+# Due to the fact that Yosys doesn't support floating parameter values
+# i.e. treats them as strings, the parameter values need to be multiplied by 1000
+# for the PLL registers to have correct values calculated during techmapping.
+proc multiply_param { cell param_name multiplier } {
+    set param_value [getparam $param_name $cell]
+    if {$param_value ne ""} {
+	set new_param_value [expr int(round($param_value * $multiplier))]
+	setparam -set $param_name $new_param_value $cell
+	puts "Updated parameter $param_name of cell $cell from $param_value to $new_param_value"
+    }
+}
+
+proc update_pll_params {} {
+    foreach cell [selection_to_tcl_list "t:PLLE2_ADV"] {
+	for {set output 0} {$output < 6} {incr output} {
+	    multiply_param $cell "CLKOUT${output}_PHASE" 1000
+	    multiply_param $cell "CLKOUT${output}_DUTY_CYCLE" 100000
+	}
+    }
+}