Skip to content

Commit

Permalink
Merge pull request #95 from mithro/ice40-top-routing-fix
Browse files Browse the repository at this point in the history 
ice40: Getting the top-routing mode working
  • Loading branch information
@mithro
mithro committed Apr 27, 2018
2 parents ed651e1 + c1d477e commit 6c6f95e
Show file tree
Hide file tree
Showing 4 changed files with 58 additions and 19 deletions.
6 changes: 4 additions & 2 deletions ice40/cells/lut_carry/lut_carry.pb_type.xml
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
<!-- set: ai sw=1 ts=1 sta et -->
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude">
<pb_type name="BLK_IG-LUT_CARRY" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">
<input name="I" num_pins="4" equivalent="false"/>
<output name="O" num_pins="1" equivalent="false"/>
<input name="FCIN" num_pins="1" equivalent="false"/>
Expand All @@ -12,7 +12,9 @@
<direct name="LUT.I[0]" input="BLK_IG-LUT_CARRY.I[0]" output="LUT.I[0]" />
<direct name="LUT.I[1]" input="BLK_IG-LUT_CARRY.I[1]" output="LUT.I[1]" />
<direct name="LUT.I[2]" input="BLK_IG-LUT_CARRY.I[2]" output="LUT.I[2]" />
<mux name="LUT.I[3]" input="BLK_IG-LUT_CARRY.I[3] BLK_IG-LUT_CARRY.FCIN" output="LUT.I[3]" />
<!-- Disable FCIN->I3 mux until https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/325 is fixed.
<mux name="LUT.I[3]" input="BLK_IG-LUT_CARRY.I[3] BLK_IG-LUT_CARRY.FCIN" output="LUT.I[3]" /> -->
<direct name="LUT.I[3]" input="BLK_IG-LUT_CARRY.I[3]" output="LUT.I[3]" />

<direct name="LUT.O" input="LUT.O" output="BLK_IG-LUT_CARRY.O" />

Expand Down
17 changes: 9 additions & 8 deletions ice40/devices/tile-routing-virt/arch.xml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,14 @@
-->
</models>

<!-- Description of the block tiles available in the iCE40 -->
<complexblocklist>
<xi:include href="tiles/plb/plb.pb_type.xml"/>
<xi:include href="tiles/ramb/ramb.pb_type.xml"/>
<xi:include href="tiles/ramt/ramt.pb_type.xml"/>
<xi:include href="../../../vpr/pad/pad.pb_type.xml"/>
</complexblocklist>

<!-- Description of the tile layouts available in the iCE40 family -->
<layout>
<xi:include href="../layouts/test4/test4.fixed_layout.xml"/>
Expand Down Expand Up @@ -98,14 +106,7 @@
<wire_switch name="1"/>
<opin_switch name="2"/>
</segment>
</segmentlist>

<!-- Description of the block tiles available in the iCE40 -->
<complexblocklist>
<xi:include href="tiles/plb/plb.pb_type.xml"/>
<xi:include href="tiles/ramb/ramb.pb_type.xml"/>
<xi:include href="tiles/ramt/ramt.pb_type.xml"/>
<xi:include href="../../../vpr/pad/pad.pb_type.xml"/>
</complexblocklist>
</segmentlist>

</architecture>
21 changes: 12 additions & 9 deletions ice40/devices/top-routing-virt/arch.xml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,9 +36,6 @@
<directlist>
<!-- Carry chain from one PLB to the next PLB -->
<direct name="CARRY" from_pin="BLK_TL-PLB.FCOUT" to_pin="BLK_TL-PLB.FCIN" x_offset="0" y_offset="-1" z_offset="0"/>
<!-- Vertical wires from neighbours -->
<direct name="sp4_r2l" from_pin="BLK_TL-PLB.o_sp4_l_v_b" to_pin="BLK_TL-PLB.i_sp4_r_v_b" x_offset="-1" y_offset="0" z_offset="0"/>
<direct name="sp4_l2r" from_pin="BLK_TL-PLB.o_sp4_r_v_b" to_pin="BLK_TL-PLB.i_sp4_l_v_b" x_offset="1" y_offset="0" z_offset="0"/>
</directlist>

<device>
Expand All @@ -60,36 +57,41 @@
</switchlist>

<segmentlist>
<!-- Global networks -->
<segment name="global" length="longline" freq="1.000000" type="bidir" Rmetal="101" Cmetal="22.5e-15">
<!-- Global networks
<segment name="global" length="longline" freq="1.000000" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<sb type="pattern">1 1</sb>
<cb type="pattern">0</cb>
<mux name="1"/>
<wire_switch name="1"/>
<opin_switch name="2"/>
</segment>
-->

<!-- Span 12 vertical tracks -->
<!-- Span 12 horizontal tracks -->
<segment name="span12" length="12" freq="1.000000" type="bidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="span12" length="12" freq="1.000000" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<sb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1</sb>
<cb type="pattern">0 0 0 0 0 0 0 0 0 0 0 0</cb>
<mux name="1"/>
<wire_switch name="1"/>
<opin_switch name="2"/>
</segment>

<!-- Span 4 vertical tracks -->
<!-- Span 4 horizontal tracks -->
<segment name="span4" length="4" freq="1.000000" type="bidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="span4" length="4" freq="1.000000" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">0 0 0 0</cb>
<mux name="1"/>
<wire_switch name="1"/>
<opin_switch name="2"/>
</segment>

<!-- Local tracks -->
<segment name="local" length="1" freq="1.000000" type="bidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="local" length="1" freq="1.000000" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<sb type="pattern">0 1</sb>
<cb type="pattern">1</cb>
<mux name="1"/>
<wire_switch name="2"/>
<opin_switch name="2"/>
</segment>
Expand All @@ -98,9 +100,10 @@
Neighbourhood tracks
*
-->
<segment name="direct" length="2" freq="1.000000" type="bidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="direct" length="2" freq="1.000000" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<sb type="pattern">0 0 0</sb>
<cb type="pattern">1 1</cb>
<mux name="1"/>
<wire_switch name="1"/>
<opin_switch name="2"/>
</segment>
Expand Down
33 changes: 33 additions & 0 deletions tests/lut_cascade_one.v
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
// 4-input LUT test.
module luta(input [3:0] I, output O);
always @(I)
case(I)
4'b1000 : O = 1;
4'b1001 : O = 1;
4'b1010 : O = 1;
4'b1100 : O = 1;
4'b1110 : O = 1;
4'b1111 : O = 1;
default : O = 0;
endcase
endmodule // top

module lutb(input [3:0] I, output O);
always @(I)
case(I)
4'b1001 : O = 1;
4'b1010 : O = 1;
4'b1100 : O = 1;
4'b1110 : O = 1;
4'b1111 : O = 1;
default : O = 0;
endcase
endmodule // top

module top(input [6:0] I, output O);
wire cascade;

luta luta_i (I[3:0], cascade);
lutb lutb_i ({cascade, I[6:3]}, O);

endmodule // top

0 comments on commit 6c6f95e

Please sign in to comment.