forked from f4pga/f4pga-arch-defs
-
Notifications
You must be signed in to change notification settings - Fork 2
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Merge pull request f4pga#2127 from kkumar23/master
Adding support for the quicklogic toolchain
- Loading branch information
Showing
9 changed files
with
138 additions
and
41 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,19 @@ | ||
| add_file_target(FILE counter_16bit.v SCANNER_TYPE verilog) | ||
|
|
||
| add_fpga_target( | ||
| NAME counter_16bit-umc22-no-adder | ||
| BOARD qlf_k4n8-qlf_k4n8_umc22_board | ||
| SOURCES counter_16bit.v | ||
| EXPLICIT_ADD_FILE_TARGET | ||
| DEFINES SYNTH_OPTS=-no_adder | ||
| ) | ||
|
|
||
| add_fpga_target( | ||
| NAME counter_16bit-umc22-adder | ||
| BOARD qlf_k4n8-qlf_k4n8_umc22_board | ||
| SOURCES counter_16bit.v | ||
| EXPLICIT_ADD_FILE_TARGET | ||
| ) | ||
|
|
||
| add_dependencies(all_qlf_k4n8_tests_no_adder counter_16bit-umc22-no-adder_route) | ||
| add_dependencies(all_qlf_k4n8_tests_adder counter_16bit-umc22-adder_route) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,2 @@ | ||
| create_clock -period 20 clk | ||
| set_clock_uncertainty 2.0 |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,18 @@ | ||
| // Description : | ||
| // Example of asimple 16 bit up counter in Verilog HDL | ||
| // | ||
| // Version 1.0 : Initial Creation | ||
| // | ||
| module counter_16bit_top (clk, reset, enable, count); | ||
| input clk, reset, enable; | ||
| output [15:0] count; | ||
| reg [15:0] count; | ||
|
|
||
| always @ (posedge clk) | ||
| if (reset == 1'b1) begin | ||
| count <= 0; | ||
| end else if ( enable == 1'b1) begin | ||
| count <= count + 1; | ||
| end | ||
|
|
||
| endmodule |
64 changes: 64 additions & 0 deletions
64
quicklogic/qlf_k4n8/tests/counter_16bit/counter_16bit_tb.v
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,64 @@ | ||
| // | ||
| // Description : | ||
| // testbench for simple 16 bit up counter in Verilog HDL | ||
| // | ||
| // | ||
|
|
||
| `timescale 10ns /10ps | ||
| `define GSIM 1 | ||
| module counter_16bit_tb; | ||
| reg clk, reset, enable; | ||
| wire [15:0] count; | ||
| reg status; | ||
|
|
||
| reg [15:0] count_compare; | ||
|
|
||
| top DUT (.clk(clk), .reset(reset), .enable(enable), .count(count)); | ||
|
|
||
| event terminate_sim; | ||
| initial begin | ||
| @ (terminate_sim); | ||
| $display("FAIL"); | ||
| #5 $fatal; | ||
| end | ||
|
|
||
| always @ (posedge clk) | ||
| if (reset == 1'b1) begin | ||
| count_compare <= 0; | ||
| end else if ( enable == 1'b1) begin | ||
| count_compare <= count_compare + 1; | ||
| end | ||
|
|
||
| initial begin | ||
| clk = 0; | ||
| reset = 1; | ||
| enable = 0; | ||
| #50 reset = 0; | ||
| #50 enable = 1; | ||
| #10 status = 0; | ||
| end | ||
|
|
||
| always | ||
| #15 clk = !clk; | ||
|
|
||
| always @ (posedge clk) | ||
| if (count_compare != count) begin | ||
| $display ("DUT Error at time %d", $time); | ||
| $display (" Expected value %d, Got Value %d", count_compare, count); | ||
| status =1; | ||
| #5 -> terminate_sim; | ||
| end | ||
|
|
||
| initial begin | ||
| $dumpfile("counter_16bit_tb.vcd"); | ||
| $dumpvars(0,counter_16bit_tb); | ||
| $display("\t\ttime,\tclk,\treset,\tenable,\tcount"); | ||
| $monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,reset,enable,count); | ||
| if(status == 1'b0) | ||
| $display("PASS"); | ||
| end | ||
|
|
||
| initial | ||
| #3000 $finish; | ||
|
|
||
| endmodule |