Merge pull request f4pga#1419 from antmicro/bufgmux_techmap

Add techmap for BUFGMUX

xc/xc7/techmap/cells_map.v

@@ -3409,6 +3409,28 @@ module BUFGCE (
   );
 endmodule
 
+module BUFGMUX (
+  input I0,
+  input I1,
+  input S,
+  output O
+  );
+
+  BUFGCTRL #(
+    .IS_CE0_INVERTED(1'b1)
+  )_TECHMAP_REPLACE_ (
+    .O(O),
+    .CE0(S),
+    .CE1(S),
+    .I0(I0),
+    .I1(I1),
+    .IGNORE0(1'b0),
+    .IGNORE1(1'b0),
+    .S0(1'b1),
+    .S1(1'b1)
+  );
+endmodule
+
 module BUFGCTRL (
 output O,
 input I0, input I1,

xc/xc7/tests/CMakeLists.txt

@@ -9,6 +9,7 @@ add_subdirectory(bram_sdp_test)
 add_subdirectory(bram_init_test)
 add_subdirectory(bram_sdp_init_test)
 add_subdirectory(bufgce)
+add_subdirectory(bufgmux)
 add_subdirectory(carry)
 add_subdirectory(simple_ff)
 add_subdirectory(dram)

xc/xc7/tests/bufgmux/CMakeLists.txt

@@ -0,0 +1,35 @@
+add_file_target(FILE bufgmux.v SCANNER_TYPE verilog)
+
+# Arty
+
+add_file_target(FILE arty.xdc)
+
+add_fpga_target(
+  NAME bufgmux_arty
+  BOARD arty-full
+  SOURCES bufgmux.v
+  INPUT_XDC_FILE arty.xdc
+  EXPLICIT_ADD_FILE_TARGET
+)
+
+add_vivado_target(
+  NAME bufgmux_arty_vivado
+  PARENT_NAME bufgmux_arty
+)
+
+# Nexys Video
+
+add_file_target(FILE nexys_video.xdc)
+
+add_fpga_target(
+  NAME bufgmux_nexys_video
+  BOARD nexys_video-mid
+  SOURCES bufgmux.v
+  INPUT_XDC_FILE nexys_video.xdc
+  EXPLICIT_ADD_FILE_TARGET
+)
+
+add_vivado_target(
+  NAME bufgmux_nexys_video_vivado
+  PARENT_NAME bufgmux_nexys_video
+)

xc/xc7/tests/bufgmux/arty.xdc

@@ -0,0 +1,8 @@
+set_property PACKAGE_PIN E3 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property PACKAGE_PIN H5 [get_ports led]
+set_property IOSTANDARD LVCMOS33 [get_ports led]
+set_property PACKAGE_PIN A8 [get_ports sw]
+set_property IOSTANDARD LVCMOS33 [get_ports sw]
+
+create_clock -period 10.0 clk

xc/xc7/tests/bufgmux/bufgmux.v

@@ -0,0 +1,75 @@
+module top (
+    input  wire clk,
+    input  wire sw,
+    output wire led
+);
+    wire O_LOCKED;
+    wire RST;
+
+    wire clk0;
+    wire clk1;
+    wire clk_out;
+    wire clk_fb_i;
+    wire clk_fb_o;
+    reg [25:0] cnt;
+
+    assign RST = 1'b0;
+
+    BUFG bufg0 (
+        .I(clk_fb_i),
+        .O(clk_fb_o)
+    );
+
+    wire clk_ibuf;
+    IBUF ibuf0 (
+        .I(clk),
+        .O(clk_ibuf)
+    );
+
+    wire clk_bufg;
+    BUFG bufg1 (
+        .I(clk_ibuf),
+        .O(clk_bufg)
+    );
+
+    PLLE2_ADV #(
+        .BANDWIDTH          ("HIGH"),
+        .COMPENSATION       ("ZHOLD"),
+
+        .CLKIN1_PERIOD      (10.0),  // 100MHz
+
+        .CLKFBOUT_MULT      (16),
+        .CLKOUT0_DIVIDE     (8),
+        .CLKOUT1_DIVIDE     (32),
+
+        .STARTUP_WAIT       ("FALSE"),
+
+        .DIVCLK_DIVIDE      (1)
+    )
+    pll (
+        .CLKIN1     (clk_bufg),
+        .CLKINSEL   (1),
+
+        .RST        (RST),
+        .PWRDWN     (0),
+        .LOCKED     (O_LOCKED),
+
+        .CLKFBIN    (clk_fb_i),
+        .CLKFBOUT   (clk_fb_o),
+
+        .CLKOUT0    (clk0),
+        .CLKOUT1    (clk1)
+    );
+
+    BUFGMUX bufgmux (
+      .I0(clk0),
+      .I1(clk1),
+      .S(sw[0]),
+      .O(clk_out)
+    );
+
+    always @(posedge clk_out) begin
+        cnt <= cnt + 1'b1;
+    end
+    assign led[0] = cnt[25];
+endmodule

xc/xc7/tests/bufgmux/nexys_video.xdc

@@ -0,0 +1,8 @@
+set_property PACKAGE_PIN R4 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property PACKAGE_PIN T14 [get_ports led]
+set_property IOSTANDARD LVCMOS25 [get_ports led]
+set_property PACKAGE_PIN E22 [get_ports sw]
+set_property IOSTANDARD LVCMOS12 [get_ports sw]
+
+create_clock -period 10.0 clk