Merge pull request f4pga#1648 from antmicro/ibex_sv2v

Add sv2v conversion to SymbiFlow build system

.github/kokoro/continuous-docs.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-continuous-docs/"
   }

.github/kokoro/continuous-ice40.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-continuous-ice40/"
   }

.github/kokoro/continuous-testarch.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-continuous-testarch/"
   }

.github/kokoro/continuous-tests.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-continuous-tests/"
   }

.github/kokoro/continuous-xc7-vendor.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     regex: "**/*.bit"
     strip_prefix: "github/symbiflow-arch-defs-continuous-xc7-vendor/"

.github/kokoro/continuous-xc7.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-continuous-xc7/"
   }

.github/kokoro/continuous-xc7a200t-vendor.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-continuous-xc7a200t-vendor/"
   }

.github/kokoro/continuous-xc7a200t.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-continuous-xc7a200t/"
   }

.github/kokoro/kokoro-cfg.py

@@ -23,6 +23,7 @@
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-%(kokoro_type)s-%(arch)s/"
   }

.github/kokoro/package_results.sh

@@ -14,6 +14,8 @@ find -name "*result*.xml" \
     -o -name "pack.log" \
     -o -name "place.log" \
     -o -name "route.log" \
+    -o -name "*_sv2v.v.log" \
+    -o -name "*.bit" \
     -o -name "*_qor.csv" \
     | xargs tar -cvf ../results.tar
 cd ..

.github/kokoro/presubmit-docs.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-presubmit-docs/"
   }

.github/kokoro/presubmit-ice40.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-presubmit-ice40/"
   }

.github/kokoro/presubmit-testarch.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-presubmit-testarch/"
   }

.github/kokoro/presubmit-tests.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-presubmit-tests/"
   }

.github/kokoro/presubmit-xc7-vendor.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     regex: "**/*.bit"
     strip_prefix: "github/symbiflow-arch-defs-presubmit-xc7-vendor/"

.github/kokoro/presubmit-xc7.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-presubmit-xc7/"
   }

.github/kokoro/presubmit-xc7a200t-vendor.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-presubmit-xc7a200t-vendor/"
   }

.github/kokoro/presubmit-xc7a200t.cfg

@@ -17,6 +17,7 @@ action {
     regex: "**/pack.log"
     regex: "**/place.log"
     regex: "**/route.log"
+    regex: "**/*_sv2v.v.log"
     regex: "**/*_qor.csv"
     strip_prefix: "github/symbiflow-arch-defs-presubmit-xc7a200t/"
   }

.gitmodules

@@ -34,3 +34,6 @@
 [submodule "third_party/symbiflow-xc-fasm2bels"]
 	path = third_party/symbiflow-xc-fasm2bels
 	url = https://github.com/SymbiFlow/symbiflow-xc-fasm2bels.git
+[submodule "third_party/ibex"]
+	path = third_party/ibex
+	url = https://github.com/lowRISC/ibex

CMakeLists.txt

@@ -11,6 +11,7 @@ include(common/cmake/v2x.cmake)
 include(common/cmake/install.cmake)
 include(common/cmake/devices.cmake)
 include(common/cmake/tools.cmake)
+include(common/cmake/sv2v.cmake)
 
 find_package(PythonInterp 3 REQUIRED)
 

common/cmake/sv2v.cmake

@@ -0,0 +1,62 @@
+# This CMake include defines the following functions:
+#
+# * ADD_SV2V_TARGET - Converts SystemVerilog sources to Verilog using sv2v
+
+function(ADD_SV2V_TARGET)
+  # ~~~
+  # ADD_SV2V_TARGET(
+  #    NAME <name>
+  #    SOURCES <source list>
+  #    FLAGS <flags>
+  #
+  # ADD_SV2V_TARGET is used for converting SystemVerilog SOURCES to Verilog.
+  # FLAGS is a string with the flags that are passed to the sv2v during the conversion.
+  #
+  # Targets  generated:
+  # * <name>_sv2v - Output sv2v file in a Verilog format.
+  #
+  # Output files:
+  #
+  # * <name>_sv2v.v - Output Verilog file
+  # * <name>_sv2v.v.log - Log file with errors and warnings during the sv2v conversion
+  #
+  # Outputs for this target will be located in the ${CMAKE_CURRENT_BINARY_DIR}
+  # ~~~
+
+  set(oneValueArgs NAME)
+  set(multiValueArgs SOURCES FLAGS)
+  cmake_parse_arguments(
+    ADD_SV2V_TARGET
+    "${options}"
+    "${oneValueArgs}"
+    "${multiValueArgs}"
+    "${ARGN}"
+  )
+
+  # Create a dependency list
+
+  set(SOURCES_DEPS "")
+  foreach(SRC ${ADD_SV2V_TARGET_SOURCES})
+    append_file_dependency(SOURCES_DEPS ${SRC})
+  endforeach()
+
+  # sv2v conversion
+
+  set(NAME ${ADD_SV2V_TARGET_NAME})
+  set(SOURCES ${ADD_SV2V_TARGET_SOURCES})
+  set(FLAGS ${ADD_SV2V_TARGET_FLAGS})
+  set(OUT_FILE ${CMAKE_CURRENT_BINARY_DIR}/${NAME}_sv2v.v)
+
+  add_custom_command(
+    OUTPUT ${OUT_FILE}
+    DEPENDS ${SOURCES_DEPS}
+    COMMAND
+      ${CMAKE_COMMAND} -E env
+      zachjs-sv2v ${FLAGS} ${SOURCES} > ${OUT_FILE} 2> ${OUT_FILE}.log
+    WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
+    VERBATIM
+  )
+  add_custom_target(${NAME}_sv2v DEPENDS ${OUT_FILE})
+
+  add_file_target(FILE ${NAME}_sv2v.v GENERATED)
+endfunction()

environment.yml

@@ -6,6 +6,7 @@ dependencies:
   - symbiflow-yosys=0.8_6021_gd8b2d1a2=20200708_083630
   - symbiflow-yosys-plugins=1.0.0.7_0060_g7454cd6=20200902_114536
   - symbiflow-vtr=8.0.0.rc2_4003_g8980e4621=20200720_145630
+  - zachjs-sv2v=0.0.5_0018_ga170536
   - cmake
   - make
   - openocd
@@ -18,3 +19,7 @@ dependencies:
   - pip
   - pip:
     - -r file:requirements.txt
+    # Ibex dependencies
+    - git+https://github.com/lowRISC/edalize.git@ot
+    - git+https://github.com/lowRISC/fusesoc.git@ot
+    - mako

requirements.txt

@@ -11,6 +11,7 @@ pycapnp==1.0.0b1
 pyjson5
 pytest
 python-constraint
+pyyaml
 scipy
 simplejson
 svgwrite

utils/fusesoc_get_sources.py

@@ -0,0 +1,41 @@
+#!/usr/bin/env python3
+
+import os
+import argparse
+
+from yaml import load, Loader
+
+SOURCE_FILE_TYPES = [
+    "verilogSource",
+    "systemVerilogSource",
+]
+
+
+def get_sources(eda_yml):
+    eda_yml_path = os.path.realpath(eda_yml)
+    current_dir = os.path.dirname(eda_yml_path)
+
+    with open(eda_yml_path) as f:
+        data = load(f, Loader=Loader)
+        files = data["files"]
+
+    for src in files:
+        if "file_type" not in src.keys():
+            continue
+
+        if src["file_type"] in SOURCE_FILE_TYPES:
+            file_path = os.path.realpath(
+                os.path.join(current_dir, src["name"])
+            )
+            basename = os.path.basename(file_path)
+            print(basename)
+
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(
+        description="Get sources from an EDA YAML file produced by fusesoc"
+    )
+    parser.add_argument("eda_yml", help="An EDA YAML produced by fusesoc")
+
+    args = parser.parse_args()
+    get_sources(args.eda_yml)