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Merge pull request f4pga#1674 from litghost/fix_carry4_plus_new_fasm2…
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Change how CARRY4 modelling is handled
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@litghost
litghost committed Oct 9, 2020
2 parents 3b7f5bf + 7ba9996 commit 9ca5fdc
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Showing 16 changed files with 1,241 additions and 342 deletions.
4 changes: 2 additions & 2 deletions common/cmake/devices.cmake
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Expand Up @@ -1375,8 +1375,7 @@ function(ADD_FPGA_TARGET)
COMMAND
${CMAKE_COMMAND} -E env
TECHMAP_PATH=${YOSYS_TECHMAP}
symbiflow-arch-defs_SOURCE_DIR=${symbiflow-arch-defs_SOURCE_DIR}
symbiflow-arch-defs_BINARY_DIR=${symbiflow-arch-defs_BINARY_DIR}
UTILS_PATH=${symbiflow-arch-defs_SOURCE_DIR}/utils
OUT_JSON=${OUT_JSON_SYNTH}
OUT_SYNTH_V=${OUT_SYNTH_V}
OUT_FASM_EXTRA=${OUT_FASM_EXTRA}
Expand All @@ -1386,6 +1385,7 @@ function(ADD_FPGA_TARGET)
USE_ROI=${USE_ROI}
PCF_FILE=${INPUT_IO_FILE}
PINMAP_FILE=${PINMAP}
PYTHON3=${PYTHON3}
${ADD_FPGA_TARGET_DEFINES}
${QUIET_CMD} ${YOSYS} -p "${COMPLETE_YOSYS_SYNTH_SCRIPT}" -l ${OUT_JSON_SYNTH}.log ${SOURCE_FILES}
COMMAND
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604 changes: 604 additions & 0 deletions utils/fix_xc7_carry.py
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29 changes: 8 additions & 21 deletions xc/common/cmake/install.cmake
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Expand Up @@ -48,27 +48,14 @@ function(DEFINE_XC_TOOLCHAIN_TARGET)
PERMISSIONS WORLD_EXECUTE WORLD_READ OWNER_WRITE OWNER_READ OWNER_EXECUTE GROUP_READ GROUP_EXECUTE)

# install python scripts
install(FILES ${symbiflow-arch-defs_SOURCE_DIR}/utils/split_inouts.py
DESTINATION bin/python
PERMISSIONS WORLD_EXECUTE WORLD_READ OWNER_WRITE OWNER_READ OWNER_EXECUTE GROUP_READ GROUP_EXECUTE)

install(FILES ${symbiflow-arch-defs_SOURCE_DIR}/xc/common/utils/prjxray_create_ioplace.py
DESTINATION bin/python
PERMISSIONS WORLD_EXECUTE WORLD_READ OWNER_WRITE OWNER_READ OWNER_EXECUTE GROUP_READ GROUP_EXECUTE)

install(FILES ${symbiflow-arch-defs_SOURCE_DIR}/xc/common/utils/prjxray_create_place_constraints.py
DESTINATION bin/python
PERMISSIONS WORLD_EXECUTE WORLD_READ OWNER_WRITE OWNER_READ OWNER_EXECUTE GROUP_READ GROUP_EXECUTE)

install(FILES ${symbiflow-arch-defs_SOURCE_DIR}/utils/vpr_io_place.py
DESTINATION bin/python
PERMISSIONS WORLD_EXECUTE WORLD_READ OWNER_WRITE OWNER_READ OWNER_EXECUTE GROUP_READ GROUP_EXECUTE)

install(FILES ${symbiflow-arch-defs_SOURCE_DIR}/utils/vpr_place_constraints.py
DESTINATION bin/python
PERMISSIONS WORLD_EXECUTE WORLD_READ OWNER_WRITE OWNER_READ OWNER_EXECUTE GROUP_READ GROUP_EXECUTE)

install(FILES ${symbiflow-arch-defs_SOURCE_DIR}/utils/eblif.py
install(FILES
${symbiflow-arch-defs_SOURCE_DIR}/utils/split_inouts.py
${symbiflow-arch-defs_SOURCE_DIR}/utils/fix_xc7_carry.py
${symbiflow-arch-defs_SOURCE_DIR}/xc/common/utils/prjxray_create_ioplace.py
${symbiflow-arch-defs_SOURCE_DIR}/xc/common/utils/prjxray_create_place_constraints.py
${symbiflow-arch-defs_SOURCE_DIR}/utils/vpr_io_place.py
${symbiflow-arch-defs_SOURCE_DIR}/utils/vpr_place_constraints.py
${symbiflow-arch-defs_SOURCE_DIR}/utils/eblif.py
DESTINATION bin/python
PERMISSIONS WORLD_EXECUTE WORLD_READ OWNER_WRITE OWNER_READ OWNER_EXECUTE GROUP_READ GROUP_EXECUTE)

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10 changes: 10 additions & 0 deletions xc/common/primitives/common_slice/carry/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,16 @@ add_file_target(
SCANNER_TYPE verilog
)

add_file_target(
FILE carry_cout_plug.sim.v
SCANNER_TYPE verilog
)

v2x(
NAME carry_cout_plug
SRCS carry_cout_plug.sim.v
)

# TODO - Switch to use V2X once FASM parameter support exists.
#v2x(
# NAME carry4_vpr
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29 changes: 14 additions & 15 deletions xc/common/primitives/common_slice/carry/carry4_vpr.model.xml
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Original file line number Diff line number Diff line change
@@ -1,23 +1,22 @@
<models xmlns:xi="http://www.w3.org/2001/XInclude">
<model name="CARRY4_VPR">
<input_ports>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 CO_FABRIC0 O3 O2 O1 O0" name="CIN"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 CO_FABRIC0 O3 O2 O1 O0" name="CYINIT"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 CO_FABRIC0 O3 O2 O1" name="DI0"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 O3 O2" name="DI1"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 O3" name="DI2"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3" name="DI3"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 CO_FABRIC0 O3 O2 O1 O0" name="S0"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 O3 O2 O1" name="S1"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 O3 O2" name="S2"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 O3" name="S3"/>
<port combinational_sink_ports="CO3 CO2 CO1 CO0 O3 O2 O1 O0" name="CIN"/>
<port combinational_sink_ports="CO3 CO2 CO1 CO0 O3 O2 O1 O0" name="CYINIT"/>
<port combinational_sink_ports="CO3 CO2 CO1 CO0 O3 O2 O1" name="DI0"/>
<port combinational_sink_ports="CO3 CO2 CO1 O3 O2" name="DI1"/>
<port combinational_sink_ports="CO3 CO2 O3" name="DI2"/>
<port combinational_sink_ports="CO3" name="DI3"/>
<port combinational_sink_ports="CO3 CO2 CO1 CO0 O3 O2 O1 O0" name="S0"/>
<port combinational_sink_ports="CO3 CO2 CO1 O3 O2 O1" name="S1"/>
<port combinational_sink_ports="CO3 CO2 O3 O2" name="S2"/>
<port combinational_sink_ports="CO3 O3" name="S3"/>
</input_ports>
<output_ports>
<port name="CO_CHAIN"/>
<port name="CO_FABRIC0"/>
<port name="CO_FABRIC1"/>
<port name="CO_FABRIC2"/>
<port name="CO_FABRIC3"/>
<port name="CO0"/>
<port name="CO1"/>
<port name="CO2"/>
<port name="CO3"/>
<port name="O0"/>
<port name="O1"/>
<port name="O2"/>
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75 changes: 32 additions & 43 deletions xc/common/primitives/common_slice/carry/carry4_vpr.pb_type.xml
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Original file line number Diff line number Diff line change
@@ -1,11 +1,10 @@
<?xml version='1.0' encoding='utf-8'?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt CARRY4_VPR" name="CARRY4_VPR" num_pb="1">
<input name="CIN" num_pins="1"/>
<output name="CO_CHAIN" num_pins="1"/>
<output name="CO_FABRIC0" num_pins="1"/>
<output name="CO_FABRIC1" num_pins="1"/>
<output name="CO_FABRIC2" num_pins="1"/>
<output name="CO_FABRIC3" num_pins="1"/>
<output name="CO0" num_pins="1"/>
<output name="CO1" num_pins="1"/>
<output name="CO2" num_pins="1"/>
<output name="CO3" num_pins="1"/>
<input name="CYINIT" num_pins="1"/>
<input name="DI0" num_pins="1"/>
<input name="DI1" num_pins="1"/>
Expand All @@ -19,44 +18,34 @@
<input name="S1" num_pins="1"/>
<input name="S2" num_pins="1"/>
<input name="S3" num_pins="1"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="DI1" max="{iopath_DI1_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="DI2" max="{iopath_DI2_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="DI3" max="{iopath_DI3_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="S0" max="{iopath_S0_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="S1" max="{iopath_S1_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="S2" max="{iopath_S2_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="S3" max="{iopath_S3_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO0}" out_port="CO_FABRIC0"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO0}" out_port="CO_FABRIC0"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO0}" out_port="CO_FABRIC0"/>
<delay_constant in_port="S0" max="{iopath_S0_CO0}" out_port="CO_FABRIC0"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="DI1" max="{iopath_DI1_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="S0" max="{iopath_S0_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="S1" max="{iopath_S1_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="DI1" max="{iopath_DI1_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="DI2" max="{iopath_DI2_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="S0" max="{iopath_S0_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="S1" max="{iopath_S1_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="S2" max="{iopath_S2_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="DI1" max="{iopath_DI0_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="DI2" max="{iopath_DI0_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="DI3" max="{iopath_DI0_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="S0" max="{iopath_S0_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="S1" max="{iopath_S1_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="S2" max="{iopath_S2_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="S3" max="{iopath_S3_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO0}" out_port="CO0"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO0}" out_port="CO0"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO0}" out_port="CO0"/>
<delay_constant in_port="S0" max="{iopath_S0_CO0}" out_port="CO0"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO1}" out_port="CO1"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO1}" out_port="CO1"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO1}" out_port="CO1"/>
<delay_constant in_port="DI1" max="{iopath_DI1_CO1}" out_port="CO1"/>
<delay_constant in_port="S0" max="{iopath_S0_CO1}" out_port="CO1"/>
<delay_constant in_port="S1" max="{iopath_S1_CO1}" out_port="CO1"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO2}" out_port="CO2"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO2}" out_port="CO2"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO2}" out_port="CO2"/>
<delay_constant in_port="DI1" max="{iopath_DI1_CO2}" out_port="CO2"/>
<delay_constant in_port="DI2" max="{iopath_DI2_CO2}" out_port="CO2"/>
<delay_constant in_port="S0" max="{iopath_S0_CO2}" out_port="CO2"/>
<delay_constant in_port="S1" max="{iopath_S1_CO2}" out_port="CO2"/>
<delay_constant in_port="S2" max="{iopath_S2_CO2}" out_port="CO2"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO3}" out_port="CO3"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO3}" out_port="CO3"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO3}" out_port="CO3"/>
<delay_constant in_port="DI1" max="{iopath_DI0_CO3}" out_port="CO3"/>
<delay_constant in_port="DI2" max="{iopath_DI0_CO3}" out_port="CO3"/>
<delay_constant in_port="DI3" max="{iopath_DI0_CO3}" out_port="CO3"/>
<delay_constant in_port="S0" max="{iopath_S0_CO3}" out_port="CO3"/>
<delay_constant in_port="S1" max="{iopath_S1_CO3}" out_port="CO3"/>
<delay_constant in_port="S2" max="{iopath_S2_CO3}" out_port="CO3"/>
<delay_constant in_port="S3" max="{iopath_S3_CO3}" out_port="CO3"/>
<delay_constant in_port="CIN" max="{iopath_CIN_O0}" out_port="O0"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_O0}" out_port="O0"/>
<delay_constant in_port="S0" max="{iopath_S0_O0}" out_port="O0"/>
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14 changes: 14 additions & 0 deletions xc/common/primitives/common_slice/carry/carry_cout_plug.sim.v
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Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
// This CARRY_COUT_PLUG actually will form a molecule with the previous
// CARRY4 primative, and allow VPR to distiguish between the net
// connecting to the next CARRY4 and the general fabric.
(* lib_whitebox *)
module CARRY_COUT_PLUG(
input CIN,
output COUT
);
(* DELAY_CONST_CIN="0" *)
wire COUT;

assign COUT = CIN;
endmodule

1 change: 1 addition & 0 deletions xc/common/primitives/common_slice/common_slice.model.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -10,5 +10,6 @@
</output_ports>
</model>
<xi:include href="carry/carry4_vpr.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="carry/carry_cout_plug.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="../ff/ff.model.xml" xpointer="xpointer(models/child::node())" />
</models>

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