Merge pull request f4pga#1506 from andrewb1999/zynq-boards

Zynq 7020 support
mithro · Jun 25, 2020 · a200ace · a200ace
2 parents 56bf647 + 612ab5a
commit a200ace
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Showing 45 changed files with 553 additions and 35 deletions.
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -293,6 +293,7 @@ add_dependencies(all_xc7_demos
     all_arty100t-full_bin
     all_basys3_bin
     all_basys3-full_bin
+    all_pynqz1-full_bin
     #all_basys3-bottom_bin
     # TODO(#548) Zybo targets not currently working, so removed from all target.
     #all_zybo_bin
@@ -306,6 +307,7 @@ add_dependencies(all_xc7_diff_fasm
     all_artix7_diff_fasm
     all_artix7_100t_diff_fasm
     all_zynq7_diff_fasm
+    all_zynq7_z020_diff_fasm
     )
 endif()
 

diff --git a/xc/xc7/archs/CMakeLists.txt b/xc/xc7/archs/CMakeLists.txt
@@ -2,3 +2,4 @@ add_subdirectory(artix7)
 add_subdirectory(artix7_100t)
 add_subdirectory(artix7_200t)
 add_subdirectory(zynq7)
+add_subdirectory(zynq7_z020)
diff --git a/xc/xc7/archs/zynq7/devices/CMakeLists.txt b/xc/xc7/archs/zynq7/devices/CMakeLists.txt
@@ -10,11 +10,3 @@ add_xc_device_define(
   PART xc7z010clg400-1
   DEVICES xc7z010
 )
-
-# Zynq 7020 contains tiles that are not present in 7010. Since we cannot have
-# different tile sets per device, this one is disabled for now.
-#add_xc7_device_define(
-#  ARCH zynq7
-#  DEVICES xc7z020
-#)
-
diff --git a/xc/xc7/archs/zynq7/tiles/cmt_top_l_upper_t/CMakeLists.txt b/xc/xc7/archs/zynq7/tiles/cmt_top_l_upper_t/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_xray_tile(
+  PART zynq7
+  TILE CMT_TOP_L_UPPER_T
+  SITE_TYPES PLLE2_ADV/PLLE2_ADV
+  EQUIVALENT_SITES CMT_TOP_L_UPPER_T
+  NO_FASM_PREFIX
+  )
diff --git a/xc/xc7/archs/zynq7/tiles/cmt_top_r_upper_t/CMakeLists.txt b/xc/xc7/archs/zynq7/tiles/cmt_top_r_upper_t/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_xray_tile(
+  PART zynq7
+  TILE CMT_TOP_R_UPPER_T
+  SITE_TYPES PLLE2_ADV/PLLE2_ADV
+  EQUIVALENT_SITES CMT_TOP_R_UPPER_T
+  NO_FASM_PREFIX
+  )
diff --git a/xc/xc7/archs/zynq7/tiles/slicel/CMakeLists.txt b/xc/xc7/archs/zynq7/tiles/slicel/CMakeLists.txt
@@ -1,5 +1,5 @@
 project_ray_tile(
-  ARCH artix7
+  ARCH zynq7
   TILE SLICEL
   SITE_AS_TILE
   SITE_TYPES SLICEL/SLICEL0

diff --git a/xc/xc7/archs/zynq7/tiles/slicem/CMakeLists.txt b/xc/xc7/archs/zynq7/tiles/slicem/CMakeLists.txt
@@ -1,8 +1,7 @@
 project_ray_tile(
-  ARCH artix7
+  ARCH zynq7
   TILE SLICEM
   SITE_AS_TILE
   SITE_TYPES SLICEM/SLICEM
-  # TODO When equivalent tiles are supported, also SLICEL will be added to EQUIVALENT_SITES
-  EQUIVALENT_SITES SLICEM
+  EQUIVALENT_SITES SLICEM SLICEL
   )
diff --git a/xc/xc7/archs/zynq7_z020/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/CMakeLists.txt
@@ -0,0 +1,22 @@
+project_ray_prepare_database(
+  PRJRAY_ARCH zynq7
+  PRJRAY_DIR ${PRJXRAY_DIR}
+  PRJRAY_DB_DIR ${PRJXRAY_DB_DIR}
+  PROTOTYPE_PART xc7z020clg484-1  
+  PARTS xc7z020clg484-1
+)
+
+add_xc_arch_define(
+  ARCH zynq7_z020
+  FAMILY xc7
+  PRJRAY_DIR ${PRJXRAY_DIR}
+  PRJRAY_DB_DIR ${PRJXRAY_DB_DIR}
+  PRJRAY_NAME prjxray
+  PRJRAY_ARCH zynq7
+  PROTOTYPE_PART xc7z020clg484-1
+  YOSYS_SYNTH_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/synth.tcl
+  YOSYS_CONV_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/conv.tcl
+)
+
+add_subdirectory(tiles)
+add_subdirectory(devices)
diff --git a/xc/xc7/archs/zynq7_z020/devices/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/devices/CMakeLists.txt
@@ -0,0 +1,6 @@
+add_xc_device_define(
+  ARCH zynq7_z020
+  PART xc7z020clg484-1
+  DEVICES xc7z020
+)
+
diff --git a/...zynq7/devices/xc7z020-virt/CMakeLists.txt → ..._z020/devices/xc7z020-virt/CMakeLists.txt b/...zynq7/devices/xc7z020-virt/CMakeLists.txt → ..._z020/devices/xc7z020-virt/CMakeLists.txt
@@ -1,5 +1,5 @@
 add_xc_device_define_type(
-  ARCH zynq7
+  ARCH zynq7_z020
   DEVICE xc7z020
   TILE_TYPES
     CLBLL_L
@@ -18,15 +18,16 @@ add_xc_device_define_type(
     CMT_TOP_L_UPPER_T
     CMT_TOP_R_UPPER_T
     HCLK_IOI3
+    PSS2
   PB_TYPES
     SLICEL
     SLICEM
     BRAM_L
     IOPAD
     IOPAD_M
     IOPAD_S
-    CLK_BUFG_BOT_R
-    CLK_BUFG_TOP_R
+    BUFGCTRL
     PLLE2_ADV
     HCLK_IOI3
+    PSS2
 )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/CMakeLists.txt
@@ -0,0 +1,34 @@
+add_subdirectory(bram_l)
+add_subdirectory(bram_r)
+add_subdirectory(clbll_l)
+add_subdirectory(clbll_r)
+add_subdirectory(clblm_l)
+add_subdirectory(clblm_r)
+add_subdirectory(slicel)
+add_subdirectory(slicem)
+add_subdirectory(clk_bufg_top_r)
+add_subdirectory(clk_bufg_bot_r)
+add_subdirectory(bufgctrl)
+add_subdirectory(hclk_ioi3)
+add_subdirectory(pss2)
+
+set(IOPAD_SITES IOB33 IDELAYE2 ILOGICE3 OLOGICE3)
+set(IOPAD_S_SITES IOB33S IDELAYE2 ILOGICE3 OLOGICE3)
+set(IOPAD_M_SITES IOB33M IDELAYE2 ILOGICE3 OLOGICE3)
+
+project_ray_equiv_tile(
+  ARCH zynq7_z020
+  TILES RIOPAD_M RIOPAD_S RIOPAD_SING LIOPAD_M LIOPAD_S LIOPAD_SING
+  PB_TYPES IOPAD IOPAD_S IOPAD_M
+  PB_TYPE_SITES IOPAD_SITES IOPAD_S_SITES IOPAD_M_SITES
+  SITE_EQUIV IOB33M=IOB33 IOB33S=IOB33
+  )
+
+set(PLLE2_ADV_SITES PLLE2_ADV)
+
+project_ray_equiv_tile(
+  ARCH zynq7_z020
+  TILES CMT_TOP_L_UPPER_T CMT_TOP_R_UPPER_T
+  PB_TYPES PLLE2_ADV
+  PB_TYPE_SITES PLLE2_ADV_SITES
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/bram_l/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/bram_l/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH zynq7_z020
+  TILE BRAM_L
+  SITE_TYPES BRAM_L/BRAM_L
+  FUSED_SITES
+  EQUIVALENT_SITES BRAM_L
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/bram_r/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/bram_r/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH zynq7_z020
+  TILE BRAM_R
+  SITE_TYPES BRAM_R/BRAM_R
+  FUSED_SITES
+  EQUIVALENT_SITES BRAM_R
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/bufgctrl/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/bufgctrl/CMakeLists.txt
@@ -0,0 +1,21 @@
+set(DEPS "")
+append_file_dependency(DEPS ${symbiflow-arch-defs_SOURCE_DIR}/xc/common/primitives/bufgctrl/bufgctrl.pb_type.xml)
+get_file_location(BUFGCTRL_PB_TYPE ${symbiflow-arch-defs_SOURCE_DIR}/xc/common/primitives/bufgctrl/bufgctrl.pb_type.xml)
+
+add_custom_command(
+  OUTPUT bufgctrl.pb_type.xml
+  COMMAND ${CMAKE_COMMAND} -E copy ${BUFGCTRL_PB_TYPE} ${CMAKE_CURRENT_BINARY_DIR}
+  DEPENDS ${DEPS}
+  )
+add_file_target(FILE bufgctrl.pb_type.xml GENERATED)
+
+set(DEPS "")
+append_file_dependency(DEPS ${symbiflow-arch-defs_SOURCE_DIR}/xc/common/primitives/bufgctrl/bufgctrl.model.xml)
+get_file_location(BUFGCTRL_MODEL ${symbiflow-arch-defs_SOURCE_DIR}/xc/common/primitives/bufgctrl/bufgctrl.model.xml)
+
+add_custom_command(
+  OUTPUT bufgctrl.model.xml
+  COMMAND ${CMAKE_COMMAND} -E copy ${BUFGCTRL_MODEL} ${CMAKE_CURRENT_BINARY_DIR}
+  DEPENDS ${DEPS}
+  )
+add_file_target(FILE bufgctrl.model.xml GENERATED)
diff --git a/xc/xc7/archs/zynq7_z020/tiles/clbll_l/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/clbll_l/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+  ARCH zynq7_z020
+  TILE CLBLL_L
+  SITE_TYPES SLICEL
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/clbll_r/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/clbll_r/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+  ARCH zynq7_z020
+  TILE CLBLL_R
+  SITE_TYPES SLICEL
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/clblm_l/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/clblm_l/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+  ARCH zynq7_z020
+  TILE CLBLM_L
+  SITE_TYPES SLICEM/SLICEL SLICEL
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/clblm_r/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/clblm_r/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+  ARCH zynq7_z020
+  TILE CLBLM_R
+  SITE_TYPES SLICEM/SLICEL SLICEL
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/clk_bufg_bot_r/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/clk_bufg_bot_r/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+    ARCH zynq7_z020
+    TILE CLK_BUFG_BOT_R
+    SITE_TYPES BUFGCTRL
+    )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/clk_bufg_top_r/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/clk_bufg_top_r/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+    ARCH zynq7_z020
+    TILE CLK_BUFG_TOP_R
+    SITE_TYPES BUFGCTRL
+    )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/cmt_top_l_upper_t/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/cmt_top_l_upper_t/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_xray_tile(
+  PART zynq7_z020
+  TILE CMT_TOP_L_UPPER_T
+  SITE_TYPES PLLE2_ADV/PLLE2_ADV
+  EQUIVALENT_SITES CMT_TOP_L_UPPER_T
+  NO_FASM_PREFIX
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/cmt_top_r_upper_t/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/cmt_top_r_upper_t/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_xray_tile(
+  PART zynq7_z020
+  TILE CMT_TOP_R_UPPER_T
+  SITE_TYPES PLLE2_ADV/PLLE2_ADV
+  EQUIVALENT_SITES CMT_TOP_R_UPPER_T
+  NO_FASM_PREFIX
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/hclk_ioi3/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/hclk_ioi3/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH zynq7_z020
+  TILE HCLK_IOI3
+  SITE_TYPES IDELAYCTRL/IDELAYCTRL
+  EQUIVALENT_SITES HCLK_IOI3
+  SITE_COORDS Y
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/int_l/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/int_l/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile(
+  ARCH zynq7_z020
+  TILE INT_L
+  SITE_TYPES TIEOFF/TIEOFF
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/int_r/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/int_r/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile(
+  ARCH zynq7_z020
+  TILE INT_R
+  SITE_TYPES TIEOFF/TIEOFF
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/liob33_sing/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/liob33_sing/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile(
+  ARCH zynq7_z020
+  TILE LIOB33_SING
+  SITE_TYPES IOB33
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/pss2/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/pss2/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH zynq7_z020
+  TILE PSS2
+  SITE_TYPES PS7/PS7
+  EQUIVALENT_SITES PSS2
+  NO_FASM_PREFIX
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/slicel/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/slicel/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH zynq7_z020
+  TILE SLICEL
+  SITE_AS_TILE
+  SITE_TYPES SLICEL/SLICEL0
+  EQUIVALENT_SITES SLICEL
+  )
diff --git a/xc/xc7/archs/zynq7_z020/tiles/slicem/CMakeLists.txt b/xc/xc7/archs/zynq7_z020/tiles/slicem/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH zynq7_z020
+  TILE SLICEM
+  SITE_AS_TILE
+  SITE_TYPES SLICEM/SLICEM
+  EQUIVALENT_SITES SLICEM SLICEL
+  )
diff --git a/xc/xc7/boards.cmake b/xc/xc7/boards.cmake
@@ -79,19 +79,41 @@ add_xc_board(
   PART xc7z010clg400-1
 )
 
+add_xc_board(
+  BOARD nexys_video
+  DEVICE xc7a200t
+  PACKAGE test
+  PART xc7a200tsbg484-1
+  PROG_TOOL ${OPENOCD_TARGET}
+  PROG_CMD "${OPENOCD} -f board/digilent_nexys_video.cfg -c \\\"init $<SEMICOLON> pld load 0 \${OUT_BIN} $<SEMICOLON> exit\\\""
+)
+
+#add_xc_board(
+#  BOARD zedboard-full
+#  DEVICE xc7z020
+#  PACKAGE test
+#  PART xc7z020clg484-1
+#)
+
 #add_xc_board(
-#  BOARD zyboz7-full
+#  BOARD microzed-full
 #  DEVICE xc7z020
 #  PACKAGE test
-#  PART xc7z020clg400-1
+#  PART xc7z020clg484-1
 #)
 
 add_xc_board(
-  BOARD nexys_video
-  DEVICE xc7a200t
+  BOARD pynqz1-full
+  DEVICE xc7z020
   PACKAGE test
-  PART xc7a200tsbg484-1
+  PART xc7z020clg400-1
   PROG_TOOL ${OPENOCD_TARGET}
-  PROG_CMD "${OPENOCD} -f board/digilent_nexys_video.cfg -c \\\"init $<SEMICOLON> pld load 0 \${OUT_BIN} $<SEMICOLON> exit\\\""
+  PROG_CMD "${OPENOCD} -f ${PRJXRAY_DIR}/utils/openocd/board-digilent-pynqz1.cfg -c \\\"init $<SEMICOLON> pld load 0 \${OUT_BIN} $<SEMICOLON> exit\\\""
 )
 
+#add_xc_board(
+#  BOARD marszx3-full
+#  DEVICE xc7z020
+#  PACKAGE test
+#  PART xc7z020clg484-1
+#)