Merge pull request f4pga#839 from litghost/add_constraints

Add constraints to scalable_proc, murax, picosoc.
mithro · Jun 19, 2019 · a71a4f2 · a71a4f2
2 parents 6e01ee6 + 6b72f6a
commit a71a4f2
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Showing 7 changed files with 55 additions and 44 deletions.
diff --git a/tests/9-scalable_proc/CMakeLists.txt b/tests/9-scalable_proc/CMakeLists.txt
@@ -75,6 +75,7 @@ function(SCALABLE_PROC)
      NAME ${TOP_NAME}
      BOARD ${SCALABLE_PROC_BOARD}
      INPUT_IO_FILE ${SCALABLE_PROC_INPUT_IO_FILE}
+     SDC_FILE ${symbiflow-arch-defs_SOURCE_DIR}/xc7/tests/common/basys3.sdc
      SOURCES
        ${ROM_FILE} processing_unit.v simpleuart.v scalable_proc.v
        ${VERILOG_TOP}

diff --git a/tests/9-soc/murax/CMakeLists.txt b/tests/9-soc/murax/CMakeLists.txt
@@ -8,6 +8,7 @@ add_file_target(FILE Murax.v SCANNER_TYPE verilog)
 add_file_target(FILE basys3_toplevel.v SCANNER_TYPE verilog)
 add_file_target(FILE hx8k-b-evn.pcf)
 add_file_target(FILE basys3.pcf)
+add_file_target(FILE basys3.sdc)
 
 if (NOT DEFINED ENV{CI} OR NOT $ENV{CI})
 add_fpga_target(
@@ -28,7 +29,15 @@ add_fpga_target(
     basys3_toplevel.v
     Murax.v
   INPUT_IO_FILE basys3.pcf
+  SDC_FILE basys3.sdc
   EXPLICIT_ADD_FILE_TARGET
 )
+
+add_vivado_target(
+    NAME murax_basys_vivado
+    PARENT_NAME murax_basys
+    CLOCK_PINS io_mainClk
+    CLOCK_PERIODS 10.0
+    )
 endif (NOT DEFINED ENV{CI} OR NOT $ENV{CI})
 
diff --git a/tests/9-soc/murax/basys3.pcf b/tests/9-soc/murax/basys3.pcf
@@ -5,6 +5,25 @@ set_io io_mainClk W5
 set_io io_uart_txd A18
 set_io io_uart_rxd B18
 
+# in[0:15] correspond with SW0-SW15 on the basys3
+set_io sw[0] V17
+set_io sw[1] V16
+set_io sw[2] W16
+set_io sw[3] W17
+set_io sw[4] W15
+set_io sw[5] V15
+set_io sw[6] W14
+set_io sw[7] W13
+set_io sw[8] V2
+set_io sw[9] T3
+set_io sw[10] T2
+set_io sw[11] R3
+set_io sw[12] W2
+set_io sw[13] U1
+set_io sw[14] T1
+set_io sw[15] R2
+
+# out[0:15] correspond with LD0-LD15 on the basys3
 set_io io_led[0] U16
 set_io io_led[1] E19
 set_io io_led[2] U19
@@ -13,3 +32,11 @@ set_io io_led[4] W18
 set_io io_led[5] U15
 set_io io_led[6] U14
 set_io io_led[7] V14
+set_io io_led[8] V13
+set_io io_led[9] V3
+set_io io_led[10] W3
+set_io io_led[11] U3
+set_io io_led[12] P3
+set_io io_led[13] N3
+set_io io_led[14] P1
+set_io io_led[15] L1
diff --git a/tests/9-soc/murax/basys3.sdc b/tests/9-soc/murax/basys3.sdc
@@ -0,0 +1 @@
+create_clock -period 10 io_mainClk
diff --git a/tests/9-soc/murax/basys3_toplevel.v b/tests/9-soc/murax/basys3_toplevel.v
@@ -4,7 +4,8 @@ module toplevel(
     input   io_mainClk,
     output  io_uart_txd,
     input   io_uart_rxd,
-    output [7:0] io_led
+    input [15:0] sw,
+    output [15:0] io_led
   );
 
   wire [31:0] io_gpioA_read;
@@ -18,7 +19,8 @@ module toplevel(
   wire io_uart_txd;
   wire io_uart_rxd;
 
-  assign io_led = io_gpioA_write[7 : 0];
+  assign io_led = io_gpioA_write[15: 0];
+  assign io_gpioA_read[15:0] = sw;
 
   Murax murax (
     .io_asyncReset(0),

diff --git a/tests/9-soc/picosoc/CMakeLists.txt b/tests/9-soc/picosoc/CMakeLists.txt
@@ -53,8 +53,9 @@ add_fpga_target(
     picorv32.v
     simpleuart.v
     progmem.v
+  SDC_FILE ${symbiflow-arch-defs_SOURCE_DIR}/xc7/tests/common/basys3.sdc
+  INPUT_IO_FILE ${symbiflow-arch-defs_SOURCE_DIR}/xc7/tests/common/basys3.pcf
   TESTBENCH_SOURCES basys3_demo_tb.v
-  INPUT_IO_FILE basys3.pcf
   EXPLICIT_ADD_FILE_TARGET
 )
 

diff --git a/tests/9-soc/picosoc/basys3_demo.v b/tests/9-soc/picosoc/basys3_demo.v
@@ -17,49 +17,23 @@
  *
  */
 
-module clk_div (
-	input clk_in,
-	output clk_out
-);
-	initial begin
-		clk_out <= 0;
-	end
-
-	always @(posedge clk_in) begin
-		clk_out <= ~clk_out;
-	end
-endmodule
-
 module basys3_demo (
 	input clk,
 
-	output ser_tx,
-	input ser_rx,
+	output tx,
+	input rx,
 
-	output [3:0] leds
+    input [15:0] sw,
+	output [15:0] led
 );
 
 	reg [5:0] reset_cnt = 0;
 	wire resetn = &reset_cnt;
 
-	always @(posedge clk_out[N_CLK_DIV-1]) begin
+	always @(posedge clk) begin
 		reset_cnt <= reset_cnt + !resetn;
 	end
 
-   /*
-	SB_IO #(
-		.PIN_TYPE(6'b 1010_01),
-		.PULLUP(1'b 0)
-	) flash_io_buf [3:0] (
-		.PACKAGE_PIN({flash_io3, flash_io2, flash_io1, flash_io0}),
-		.OUTPUT_ENABLE({flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}),
-		.D_OUT_0({flash_io3_do, flash_io2_do, flash_io1_do, flash_io0_do}),
-		.D_IN_0({flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di})
-	);
-	*/
-
-	localparam integer N_CLK_DIV = 2;
-
 	wire        iomem_valid;
 	reg         iomem_ready;
 	wire [3:0]  iomem_wstrb;
@@ -68,18 +42,17 @@ module basys3_demo (
 	reg  [31:0] iomem_rdata;
 
 	reg [31:0] gpio;
-	reg [N_CLK_DIV-1:0] clk_out;
 
-	assign leds = gpio[3:0];
+	assign led = gpio[15:0];
 
-	always @(posedge clk_out[N_CLK_DIV-1]) begin
+	always @(posedge clk) begin
 		if (!resetn) begin
 			gpio <= 0;
 		end else begin
 			iomem_ready <= 0;
 			if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
 				iomem_ready <= 1;
-				iomem_rdata <= gpio;
+				iomem_rdata <= {sw, gpio[15:0]};
 				if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
 				if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
 				if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
@@ -89,11 +62,11 @@ module basys3_demo (
 	end
 
 	picosoc_noflash soc (
-		.clk          (clk_out[N_CLK_DIV-1]),
+		.clk          (clk),
 		.resetn       (resetn      ),
 
-		.ser_tx       (ser_tx      ),
-		.ser_rx       (ser_rx      ),
+		.ser_tx       (tx),
+		.ser_rx       (rx),
 
 		.irq_5        (1'b0        ),
 		.irq_6        (1'b0        ),
@@ -107,7 +80,4 @@ module basys3_demo (
 		.iomem_rdata  (iomem_rdata )
 	);
 
-	clk_div clk_div_0 (.clk_in(clk), .clk_out(clk_out[0]));
-	clk_div clk_div_1 (.clk_in(clk_out[0]), .clk_out(clk_out[1]));
-
 endmodule