Merge pull request f4pga#943 from antmicro/fasm2v_carry4_fix

Fix unconnected CARRY4 inputs in fasm2bels
mithro · Aug 14, 2019 · b479a08 · b479a08
2 parents 68a3e2c + 05712b8
commit b479a08
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/xc7/fasm2bels/clb_models.py b/xc7/fasm2bels/clb_models.py
@@ -669,18 +669,18 @@ def connect_ce_sr(bel, ce, sr):
 
         if site.has_feature('PRECYINIT.AX'):
             site.add_sink(bel, 'CYINIT', 'AX')
-            bel.unused_connections.add('CI')
+            bel.connections['CI'] = 0
 
         elif site.has_feature('PRECYINIT.C0'):
             bel.connections['CYINIT'] = 0
-            bel.unused_connections.add('CI')
+            bel.connections['CI'] = 0
 
         elif site.has_feature('PRECYINIT.C1'):
             bel.connections['CYINIT'] = 1
-            bel.unused_connections.add('CI')
+            bel.connections['CI'] = 0
 
         elif site.has_feature('PRECYINIT.CIN'):
-            bel.unused_connections.add('CYINIT')
+            bel.connections['CYINIT'] = 0
             site.add_sink(bel, 'CI', 'CIN')
 
         else: