Merge pull request f4pga#1563 from tcal-x/staging100T_with_litex

New 100t LiteX test (soc/litex/base)
mithro · Jul 8, 2020 · c5c86dd · c5c86dd
2 parents a51bd8c + 023259b
commit c5c86dd
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diff --git a/xc/xc7/tests/soc/litex/base/CMakeLists.txt b/xc/xc7/tests/soc/litex/base/CMakeLists.txt
@@ -3,7 +3,11 @@ add_file_target(FILE mem_1.init)
 add_file_target(FILE mem_2.init)
 add_file_target(FILE arty.sdc)
 add_file_target(FILE arty_clocks.xdc)
+add_file_target(FILE arty.pcf)
+add_file_target(FILE baselitex_arty.xdc)
 
+add_file_target(FILE VexRiscv_Linux.v SCANNER_TYPE verilog)
+add_file_target(FILE baselitex_arty.v SCANNER_TYPE verilog)
 add_fpga_target(
   NAME baselitex_arty
   BOARD arty-full
@@ -13,10 +17,30 @@ add_fpga_target(
   INPUT_IO_FILE arty.pcf
   INPUT_XDC_FILE baselitex_arty.xdc
   SDC_FILE arty.sdc
+  EXPLICIT_ADD_FILE_TARGET
 )
 
 add_vivado_target(
     NAME baselitex_arty_vivado
     PARENT_NAME baselitex_arty
     XDC arty_clocks.xdc
 )
+
+add_file_target(FILE baselitex_arty100t.v SCANNER_TYPE verilog)
+add_fpga_target(
+  NAME baselitex_arty100t
+  BOARD arty100t-full
+  SOURCES
+    baselitex_arty100t.v
+    VexRiscv_Linux.v
+  INPUT_IO_FILE arty.pcf
+  INPUT_XDC_FILE baselitex_arty.xdc
+  SDC_FILE arty.sdc
+  EXPLICIT_ADD_FILE_TARGET
+)
+
+add_vivado_target(
+    NAME baselitex_arty100t_vivado
+    PARENT_NAME baselitex_arty100t
+    XDC arty_clocks.xdc
+)
diff --git a/xc/xc7/tests/soc/litex/base/README.md b/xc/xc7/tests/soc/litex/base/README.md
@@ -23,3 +23,7 @@ export CPU_VARIANT=linux
 export PLATFORM=arty
 export FIRMWARE=linux
 ```
+
+To create `baselitex_arty100t.v`, copy from `baselitex_arty.v` and then make the following edits:
+* *Add* constraint `(* LOC="PLLE2_ADV_X1Y1" *)` to instance `PLLE2_ADV`.
+* *Change* constraint `(* LOC="IDELAYCTRL_X1Y0" *)` to `(* LOC="IDELAYCTRL_X1Y1" *)` on instance `IDELAYCTRL`.