Merge pull request f4pga#2116 from antmicro/add-pcie-complex-test

Add PCIe complex test
mithro · Apr 22, 2021 · cc76574 · cc76574
2 parents f0de963 + 7eb70a3
commit cc76574
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Showing 9 changed files with 843 additions and 0 deletions.
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -171,6 +171,7 @@ add_dependencies(all_xc7_demos
     all_arty-uart_bin
     all_arty-full_bin
     all_arty100t-full_bin
+    all_netv2-a100t_bin
     all_basys3_bin
     all_basys3-full_bin
     all_pynqz1-full_bin

diff --git a/xc/xc7/boards.cmake b/xc/xc7/boards.cmake
@@ -96,6 +96,13 @@ add_xc_board(
   PART xc7a100tcsg324-1
 )
 
+add_xc_board(
+  BOARD netv2-a100t
+  DEVICE xc7a100t
+  PACKAGE test
+  PART xc7a100tfgg484-2
+)
+
 # TODO: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/344
 add_xc_board(
   BOARD zybo

diff --git a/xc/xc7/techmap/cells_map.v b/xc/xc7/techmap/cells_map.v
@@ -7011,6 +7011,8 @@ module GTPE2_COMMON (
   parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
   parameter [0:0] IS_PLL0LOCKDETCLK_INVERTED = 1'b0;
   parameter [0:0] IS_PLL1LOCKDETCLK_INVERTED = 1'b0;
+  parameter [0:0] IS_GTGREFCLK0_INVERTED = 1'b0;
+  parameter [0:0] IS_GTGREFCLK1_INVERTED = 1'b0;
 
   parameter _TECHMAP_CONSTMSK_DRPCLK_         = 0;
   parameter _TECHMAP_CONSTVAL_DRPCLK_         = 0;

diff --git a/xc/xc7/tests/CMakeLists.txt b/xc/xc7/tests/CMakeLists.txt
@@ -43,3 +43,4 @@ add_subdirectory(idelayctrl)
 add_subdirectory(gtp_common)
 add_subdirectory(gtp_channel)
 add_subdirectory(pcie)
+add_subdirectory(pcie_complex)
diff --git a/xc/xc7/tests/common/CMakeLists.txt b/xc/xc7/tests/common/CMakeLists.txt
@@ -31,6 +31,9 @@ add_file_target(FILE nexys_video.xdc)
 add_file_target(FILE nexys_video_noclk.xdc)
 add_file_target(FILE nexys_video_gtp_channel.pcf)
 
+# NeTV2 xc7a100t variant constraint files
+add_file_target(FILE netv2_a100t_pcie_complex.xdc)
+
 add_file_target(FILE error_output_logic.v SCANNER_TYPE verilog)
 add_file_target(FILE error_output_logic_unt.v SCANNER_TYPE verilog)
 add_file_target(FILE error_output_logic_tb.v SCANNER_TYPE verilog)

diff --git a/xc/xc7/tests/common/netv2_a100t_pcie_complex.xdc b/xc/xc7/tests/common/netv2_a100t_pcie_complex.xdc
@@ -0,0 +1,28 @@
+# pcie_pipe_clk
+set_property LOC J19 [get_ports {pcie_pipe_clk}]
+set_property IOSTANDARD LVCMOS33 [get_ports {pcie_pipe_clk}]
+
+# pcie_rst_n
+set_property LOC E18 [get_ports {pcie_rst_n}]
+set_property IOSTANDARD LVCMOS33 [get_ports {pcie_rst_n}]
+
+# pcie_clk_p
+set_property LOC F6 [get_ports {pcie_clk_p}]
+
+# pcie_clk_n
+set_property LOC E6 [get_ports {pcie_clk_n}]
+
+# pcie_rx_p
+set_property LOC B8 [get_ports {pcie_rx_p}]
+
+# pcie_rx_n
+set_property LOC A8 [get_ports {pcie_rx_n}]
+
+# pcie_tx_p
+set_property LOC B4 [get_ports {pcie_tx_p}]
+
+# pcie_tx_n
+set_property LOC A4 [get_ports {pcie_tx_n}]
+
+# drprdy
+set_property LOC P20 [get_ports {drprdy}]
diff --git a/xc/xc7/tests/pcie_complex/CMakeLists.txt b/xc/xc7/tests/pcie_complex/CMakeLists.txt
@@ -0,0 +1,9 @@
+add_file_target(FILE pcie_complex.v SCANNER_TYPE verilog)
+
+add_fpga_target(
+  NAME pcie_complex_netv2_a100t
+  BOARD netv2-a100t
+  INPUT_XDC_FILE ${COMMON}/netv2_a100t_pcie_complex.xdc
+  SOURCES pcie_complex.v
+  EXPLICIT_ADD_FILE_TARGET
+  )
diff --git a/xc/xc7/tests/pcie_complex/README.md b/xc/xc7/tests/pcie_complex/README.md
@@ -0,0 +1,5 @@
+PCIe complex test
+=================
+
+This test is intended to check the correct P&R flow and bitstream generation
+for a design with GTP and PCIe blocks.