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Merge pull request f4pga#656 from HackerFoo/ram128-rename
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{S,D}PRAM128 rename
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@mithro
mithro committed Apr 29, 2019
2 parents 83869fc + 827fe83 commit dc45861
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Showing 10 changed files with 140 additions and 140 deletions.
4 changes: 2 additions & 2 deletions xc7/primitives/slicem/Ndram/CMakeLists.txt
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Expand Up @@ -2,8 +2,8 @@ add_file_target(FILE dpram32.pb_type.xml SCANNER_TYPE xml)
add_file_target(FILE spram32.pb_type.xml SCANNER_TYPE xml)
add_file_target(FILE dpram64.pb_type.xml SCANNER_TYPE xml)
add_file_target(FILE spram64.pb_type.xml SCANNER_TYPE xml)
add_file_target(FILE dpram128.pb_type.xml SCANNER_TYPE xml)
add_file_target(FILE spram128.pb_type.xml SCANNER_TYPE xml)
add_file_target(FILE dpram64_for_ram128x1d.pb_type.xml SCANNER_TYPE xml)
add_file_target(FILE spram64_for_ram128x1s.pb_type.xml SCANNER_TYPE xml)

add_file_target(FILE ntemplate.N_dram.pb_type.xml SCANNER_TYPE xml)
add_file_target(FILE ntemplate.N_dram128.pb_type.xml SCANNER_TYPE xml)
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14 changes: 7 additions & 7 deletions xc7/primitives/slicem/Ndram/d_dram128.pb_type.xml
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Expand Up @@ -8,15 +8,15 @@
<output name="O6" num_pins="1" />

<mode name="128_SINGLE_PORT">
<xi:include href="spram128.pb_type.xml" />
<xi:include href="spram64_for_ram128x1s.pb_type.xml" />
<interconnect>
<direct name="CLK" input="D_DRAM128.CLK" output="SPRAM128.CLK" />
<direct name="A" input="D_DRAM128.A" output="SPRAM128.A" />
<direct name="WA7" input="D_DRAM128.WA7" output="SPRAM128.WA7" />
<direct name="DI" input="D_DRAM128.DI1" output="SPRAM128.DI1" />
<direct name="WE" input="D_DRAM128.WE" output="SPRAM128.WE" />
<direct name="CLK" input="D_DRAM128.CLK" output="SPRAM64_for_RAM128X1S.CLK" />
<direct name="A" input="D_DRAM128.A" output="SPRAM64_for_RAM128X1S.A" />
<direct name="WA7" input="D_DRAM128.WA7" output="SPRAM64_for_RAM128X1S.WA7" />
<direct name="DI" input="D_DRAM128.DI1" output="SPRAM64_for_RAM128X1S.DI1" />
<direct name="WE" input="D_DRAM128.WE" output="SPRAM64_for_RAM128X1S.WE" />

<direct name="O6" input="SPRAM128.O6" output="D_DRAM128.O6" />
<direct name="O6" input="SPRAM64_for_RAM128X1S.O6" output="D_DRAM128.O6" />
</interconnect>
</mode>

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52 changes: 0 additions & 52 deletions xc7/primitives/slicem/Ndram/dpram128.pb_type.xml
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52 changes: 52 additions & 0 deletions xc7/primitives/slicem/Ndram/dpram64_for_ram128x1d.pb_type.xml
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@@ -0,0 +1,52 @@
<!-- Single port 64x1 DRAM. Used in 128x1 modes.
This pb_type is the same as SPRAM64, except that WA7USED is set.
Because WA7USED is a slice wide, the upper and lower DRAMs must be in
128-bit. This special casing is not required for 256x1 mode because it
always consumes the entire slice, so there is no ambiguity.
-->
<pb_type name="DPRAM64_for_RAM128X1D" num_pb="1" blif_model=".subckt DPRAM64_for_RAM128X1D">
<clock name="CLK" num_pins="1" />

<!-- A1 - Read port -->
<input name="A" num_pins="6" />
<output name="O6" num_pins="1" />

<delay_matrix type="max" in_port="DPRAM64_for_RAM128X1D.A" out_port="DPRAM64_for_RAM128X1D.O6">
0.068e-9
0.068e-9
0.068e-9
0.068e-9
0.068e-9
0.068e-9
</delay_matrix>

<!-- B1 - Write Port -->
<input name="WA" num_pins="6" />
<input name="WA7" num_pins="1" />
<input name="DI1" num_pins="1" />
<input name="WE" num_pins="1" />

<T_setup value="10e-12" port="DPRAM64_for_RAM128X1D.WA" clock="CLK" />
<T_clock_to_Q max="10e-12" port="DPRAM64_for_RAM128X1D.WA" clock="CLK" />
<delay_constant max="10e-12" in_port="DPRAM64_for_RAM128X1D.WA" out_port="DPRAM64_for_RAM128X1D.O6" />
<T_setup value="10e-12" port="DPRAM64_for_RAM128X1D.WA7" clock="CLK" />
<T_clock_to_Q max="10e-12" port="DPRAM64_for_RAM128X1D.WA7" clock="CLK" />
<delay_constant max="10e-12" in_port="DPRAM64_for_RAM128X1D.WA7" out_port="DPRAM64_for_RAM128X1D.O6" />
<T_setup value="10e-12" port="DPRAM64_for_RAM128X1D.WE" clock="CLK" />
<T_clock_to_Q max="10e-12" port="DPRAM64_for_RAM128X1D.WE" clock="CLK" />
<delay_constant max="10e-12" in_port="DPRAM64_for_RAM128X1D.WE" out_port="DPRAM64_for_RAM128X1D.O6" />
<T_setup value="10e-12" port="DPRAM64_for_RAM128X1D.DI1" clock="CLK" />
<T_clock_to_Q max="10e-12" port="DPRAM64_for_RAM128X1D.DI1" clock="CLK" />
<delay_constant max="10e-12" in_port="DPRAM64_for_RAM128X1D.DI1" out_port="DPRAM64_for_RAM128X1D.O6" />
<metadata>
<meta name="fasm_params">
INIT[63:0] = INIT
</meta>
<meta name="fasm_features">
RAM
</meta>
<meta name="type">bel</meta>
<meta name="subtype">memory</meta>
</metadata>
</pb_type>
4 changes: 2 additions & 2 deletions xc7/primitives/slicem/Ndram/ntemplate.N_dram.model.xml
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Expand Up @@ -6,7 +6,7 @@
</input_ports>
<output_ports/>
</model>
<model name="DPRAM128">
<model name="DPRAM64_for_RAM128X1D">
<input_ports>
<port is_clock="1" name="CLK" />
<port clock="CLK" name="WE" combinational_sink_ports="O6" />
Expand All @@ -20,7 +20,7 @@
<port name="O6" />
</output_ports>
</model>
<model name="SPRAM128">
<model name="SPRAM64_for_RAM128X1S">
<input_ports>
<port is_clock="1" name="CLK" />
<port clock="CLK" name="WE" combinational_sink_ports="O6" />
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34 changes: 17 additions & 17 deletions xc7/primitives/slicem/Ndram/ntemplate.N_dram128.pb_type.xml
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Expand Up @@ -14,36 +14,36 @@
<output name="DI_OUT" num_pins="1" />

<mode name="128_DUAL_PORT">
<xi:include href="dpram128.pb_type.xml" />
<xi:include href="dpram64_for_ram128x1d.pb_type.xml" />
<interconnect>
<direct name="CLK" input="{N}_DRAM128.CLK" output="DPRAM128.CLK" />
<direct name="A" input="{N}_DRAM128.A" output="DPRAM128.A" />
<direct name="WA" input="{N}_DRAM128.WA[5:0]" output="DPRAM128.WA[5:0]" />
<direct name="WA7" input="{N}_DRAM128.WA[6]" output="DPRAM128.WA7" />
<direct name="{N}I" input="{N}_DRAM128.PARENT_DI" output="DPRAM128.DI1" />
<direct name="WE" input="{N}_DRAM128.WE" output="DPRAM128.WE" />
<direct name="CLK" input="{N}_DRAM128.CLK" output="DPRAM64_for_RAM128X1D.CLK" />
<direct name="A" input="{N}_DRAM128.A" output="DPRAM64_for_RAM128X1D.A" />
<direct name="WA" input="{N}_DRAM128.WA[5:0]" output="DPRAM64_for_RAM128X1D.WA[5:0]" />
<direct name="WA7" input="{N}_DRAM128.WA[6]" output="DPRAM64_for_RAM128X1D.WA7" />
<direct name="{N}I" input="{N}_DRAM128.PARENT_DI" output="DPRAM64_for_RAM128X1D.DI1" />
<direct name="WE" input="{N}_DRAM128.WE" output="DPRAM64_for_RAM128X1D.WE" />

<direct name="DO6" input="DPRAM128.O6" output="{N}_DRAM128.DO6" />
<direct name="O6" input="DPRAM128.O6" output="{N}_DRAM128.O6" />
<direct name="DO6" input="DPRAM64_for_RAM128X1D.O6" output="{N}_DRAM128.DO6" />
<direct name="O6" input="DPRAM64_for_RAM128X1D.O6" output="{N}_DRAM128.O6" />
<direct name="DI_OUT" input="{N}_DRAM128.PARENT_DI" output="{N}_DRAM128.DI_OUT" />
</interconnect>
</mode>
<mode name="128_SINGLE_PORT">
<xi:include href="spram128.pb_type.xml" />
<xi:include href="spram64_for_ram128x1s.pb_type.xml" />
<metadata>
<meta name="fasm_features">
DI1MUX.{N}I
</meta>
</metadata>
<interconnect>
<direct name="CLK" input="{N}_DRAM128.CLK" output="SPRAM128.CLK" />
<direct name="A" input="{N}_DRAM128.A" output="SPRAM128.A" />
<direct name="WA7" input="{N}_DRAM128.WA[6]" output="SPRAM128.WA7" />
<direct name="{N}I" input="{N}_DRAM128.{N}I" output="SPRAM128.DI1" />
<direct name="WE" input="{N}_DRAM128.WE" output="SPRAM128.WE" />
<direct name="CLK" input="{N}_DRAM128.CLK" output="SPRAM64_for_RAM128X1S.CLK" />
<direct name="A" input="{N}_DRAM128.A" output="SPRAM64_for_RAM128X1S.A" />
<direct name="WA7" input="{N}_DRAM128.WA[6]" output="SPRAM64_for_RAM128X1S.WA7" />
<direct name="{N}I" input="{N}_DRAM128.{N}I" output="SPRAM64_for_RAM128X1S.DI1" />
<direct name="WE" input="{N}_DRAM128.WE" output="SPRAM64_for_RAM128X1S.WE" />

<direct name="SO6" input="SPRAM128.O6" output="{N}_DRAM128.SO6" />
<direct name="O6" input="SPRAM128.O6" output="{N}_DRAM128.O6" />
<direct name="SO6" input="SPRAM64_for_RAM128X1S.O6" output="{N}_DRAM128.SO6" />
<direct name="O6" input="SPRAM64_for_RAM128X1S.O6" output="{N}_DRAM128.O6" />
<direct name="DI_OUT" input="{N}_DRAM128.{N}I" output="{N}_DRAM128.DI_OUT" />
</interconnect>
</mode>
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51 changes: 0 additions & 51 deletions xc7/primitives/slicem/Ndram/spram128.pb_type.xml
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51 changes: 51 additions & 0 deletions xc7/primitives/slicem/Ndram/spram64_for_ram128x1s.pb_type.xml
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@@ -0,0 +1,51 @@
<!-- Single port 64x1 DRAM. Used in 128x1 modes.
This pb_type is the same as SPRAM64, except that WA7USED is set.
Because WA7USED is a slice wide, the upper and lower DRAMs must be in
128-bit. This special casing is not required for 256x1 mode because it
always consumes the entire slice, so there is no ambiguity.
-->
<pb_type name="SPRAM64_for_RAM128X1S" num_pb="1" blif_model=".subckt SPRAM64_for_RAM128X1S">
<clock name="CLK" num_pins="1" />

<!-- A - Read/write port -->
<input name="A" num_pins="6" />
<input name="WA7" num_pins="1" />
<input name="DI1" num_pins="1" />
<input name="WE" num_pins="1" />

<output name="O6" num_pins="1" />

<delay_matrix type="max" in_port="SPRAM64_for_RAM128X1S.A" out_port="SPRAM64_for_RAM128X1S.O6">
0.068e-9
0.068e-9
0.068e-9
0.068e-9
0.068e-9
0.068e-9
</delay_matrix>

<!-- B1 - Write Port -->

<T_setup value="10e-12" port="SPRAM64_for_RAM128X1S.A" clock="CLK" />
<T_clock_to_Q max="10e-12" port="SPRAM64_for_RAM128X1S.A" clock="CLK" />
<T_setup value="10e-12" port="SPRAM64_for_RAM128X1S.WA7" clock="CLK" />
<T_clock_to_Q max="10e-12" port="SPRAM64_for_RAM128X1S.WA7" clock="CLK" />
<delay_constant max="10e-12" in_port="SPRAM64_for_RAM128X1S.WA7" out_port="SPRAM64_for_RAM128X1S.O6" />
<T_setup value="10e-12" port="SPRAM64_for_RAM128X1S.WE" clock="CLK" />
<T_clock_to_Q max="10e-12" port="SPRAM64_for_RAM128X1S.WE" clock="CLK" />
<delay_constant max="10e-12" in_port="SPRAM64_for_RAM128X1S.WE" out_port="SPRAM64_for_RAM128X1S.O6" />
<T_setup value="10e-12" port="SPRAM64_for_RAM128X1S.DI1" clock="CLK" />
<T_clock_to_Q max="10e-12" port="SPRAM64_for_RAM128X1S.DI1" clock="CLK" />
<delay_constant max="10e-12" in_port="SPRAM64_for_RAM128X1S.DI1" out_port="SPRAM64_for_RAM128X1S.O6" />
<metadata>
<meta name="fasm_params">
INIT[63:0] = INIT
</meta>
<meta name="fasm_features">
RAM
</meta>
<meta name="type">bel</meta>
<meta name="subtype">memory</meta>
</metadata>
</pb_type>
14 changes: 7 additions & 7 deletions xc7/techmap/cells_map.v
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Expand Up @@ -272,15 +272,15 @@ module RAM128X1S (

wire [5:0] A = {A5, A4, A3, A2, A1, A0};

// SPRAM128 is used here because RAM128X1S only consumes half of the
// SPRAM64_for_RAM128X1S is used here because RAM128X1S only consumes half of the
// slice, but WA7USED is slice wide. The packer should be able to pack two
// RAM128X1S in a slice, but it should not be able to pack RAM128X1S and
// a RAM64X1[SD]. It is unclear if RAM32X1[SD] or RAM32X2S can be packed
// with a RAM128X1S, so for now it is forbidden.
//
// Note that a RAM128X1D does not require [SD]PRAM128 because it consumes
// the entire slice.
SPRAM128 #(
SPRAM64_for_RAM128X1S #(
.INIT(INIT[63:0]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
Expand All @@ -293,7 +293,7 @@ module RAM128X1S (
.O6(low_lut_o6)
);

DPRAM128 #(
DPRAM64_for_RAM128X1D #(
.INIT(INIT[127:64]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(1)
Expand Down Expand Up @@ -322,7 +322,7 @@ module RAM128X1D (
wire blut_o6;
wire alut_o6;

SPRAM128 #(
SPRAM64_for_RAM128X1S #(
.INIT(INIT[63:0]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
Expand All @@ -335,7 +335,7 @@ module RAM128X1D (
.O6(dlut_o6)
);

DPRAM128 #(
DPRAM64_for_RAM128X1D #(
.INIT(INIT[127:64]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(1)
Expand All @@ -349,7 +349,7 @@ module RAM128X1D (
.O6(clut_o6)
);

DPRAM128 #(
DPRAM64_for_RAM128X1D #(
.INIT(INIT[63:0]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
Expand All @@ -363,7 +363,7 @@ module RAM128X1D (
.O6(blut_o6)
);

DPRAM128 #(
DPRAM64_for_RAM128X1D #(
.INIT(INIT[127:64]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
Expand Down
4 changes: 2 additions & 2 deletions xc7/techmap/cells_sim.v
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Expand Up @@ -87,7 +87,7 @@ endmodule
// ============================================================================
// Distributed RAMs

module DPRAM128 (
module DPRAM64_for_RAM128X1D (
output O6,
input DI1, CLK, WE, WA7,
input [5:0] A, WA
Expand All @@ -104,7 +104,7 @@ module DPRAM128 (
always @(posedge clk) if (WE & (WA7 == HIGH_WA7_SELECT)) mem[WA] <= DI1;
endmodule

module SPRAM128 (
module SPRAM64_for_RAM128X1S (
output O6,
input DI1, CLK, WE, WA7,
input [5:0] A
Expand Down

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