Add RAM units (#3)

* Add RAM units (8, 64, 512, 4K, 16K) * Skip RAM4K/16K test when using CPython
mlouielu · Jul 4, 2017 · d5f7207 · d5f7207
1 parent 87412d3
commit d5f7207
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Showing 11 changed files with 1,689 additions and 8 deletions.
diff --git a/nand2vm/seq/__init__.py b/nand2vm/seq/__init__.py
@@ -8,3 +8,4 @@
 from .dff import DFF
 from .bit import Bit
 from .register import Register
+from .ram import RAM8, RAM64, RAM512, RAM4K, RAM16K
diff --git a/nand2vm/seq/ram.py b/nand2vm/seq/ram.py
@@ -0,0 +1,157 @@
+#
+# Copyright (c) 2017 Louie Lu. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+
+from .clock import ClockPhase
+from .register import Register
+from .. import gate
+from ..bitarray import BitArray
+
+
+class RAM8(object):
+
+    def __init__(self):
+        self.a = Register()
+        self.b = Register()
+        self.c = Register()
+        self.d = Register()
+        self.e = Register()
+        self.f = Register()
+        self.g = Register()
+        self.h = Register()
+        self.clock = ClockPhase.HIGH
+
+    def update(self, source: BitArray, load: bool, address: BitArray,
+               clock: ClockPhase=None) -> BitArray:
+        if clock:
+            self.clock = clock
+        al, bl, cl, dl, el, fl, gl, hl = gate.DMux8Way(load, address)
+        return gate.Mux8Way16(
+            self.a.update(source, al, clock=self.clock),
+            self.b.update(source, bl, clock=self.clock),
+            self.c.update(source, cl, clock=self.clock),
+            self.d.update(source, dl, clock=self.clock),
+            self.e.update(source, el, clock=self.clock),
+            self.f.update(source, fl, clock=self.clock),
+            self.g.update(source, gl, clock=self.clock),
+            self.h.update(source, hl, clock=self.clock),
+            select=address[:3]
+        )
+
+
+class RAM64(object):
+
+    def __init__(self):
+        self.a = RAM8()
+        self.b = RAM8()
+        self.c = RAM8()
+        self.d = RAM8()
+        self.e = RAM8()
+        self.f = RAM8()
+        self.g = RAM8()
+        self.h = RAM8()
+        self.clock = ClockPhase.HIGH
+
+    def update(self, source: BitArray, load: bool, address: BitArray,
+               clock: ClockPhase=None) -> BitArray:
+        if clock:
+            self.clock = clock
+        al, bl, cl, dl, el, fl, gl, hl = gate.DMux8Way(load, address[:3])
+        return gate.Mux8Way16(
+            self.a.update(source, al, address[3: 6], clock=self.clock),
+            self.b.update(source, bl, address[3: 6], clock=self.clock),
+            self.c.update(source, cl, address[3: 6], clock=self.clock),
+            self.d.update(source, dl, address[3: 6], clock=self.clock),
+            self.e.update(source, el, address[3: 6], clock=self.clock),
+            self.f.update(source, fl, address[3: 6], clock=self.clock),
+            self.g.update(source, gl, address[3: 6], clock=self.clock),
+            self.h.update(source, hl, address[3: 6], clock=self.clock),
+            select=address[:3]
+        )
+
+
+class RAM512(object):
+
+    def __init__(self):
+        self.a = RAM64()
+        self.b = RAM64()
+        self.c = RAM64()
+        self.d = RAM64()
+        self.e = RAM64()
+        self.f = RAM64()
+        self.g = RAM64()
+        self.h = RAM64()
+        self.clock = ClockPhase.HIGH
+
+    def update(self, source: BitArray, load: bool, address: BitArray,
+               clock: ClockPhase=None) -> BitArray:
+        if clock:
+            self.clock = clock
+        al, bl, cl, dl, el, fl, gl, hl = gate.DMux8Way(load, address[:3])
+        return gate.Mux8Way16(
+            self.a.update(source, al, address[3: 9], clock=self.clock),
+            self.b.update(source, bl, address[3: 9], clock=self.clock),
+            self.c.update(source, cl, address[3: 9], clock=self.clock),
+            self.d.update(source, dl, address[3: 9], clock=self.clock),
+            self.e.update(source, el, address[3: 9], clock=self.clock),
+            self.f.update(source, fl, address[3: 9], clock=self.clock),
+            self.g.update(source, gl, address[3: 9], clock=self.clock),
+            self.h.update(source, hl, address[3: 9], clock=self.clock),
+            select=address[:3]
+        )
+
+
+class RAM4K(object):
+
+    def __init__(self):
+        self.a = RAM512()
+        self.b = RAM512()
+        self.c = RAM512()
+        self.d = RAM512()
+        self.e = RAM512()
+        self.f = RAM512()
+        self.g = RAM512()
+        self.h = RAM512()
+        self.clock = ClockPhase.HIGH
+
+    def update(self, source: BitArray, load: bool, address: BitArray,
+               clock: ClockPhase=None) -> BitArray:
+        if clock:
+            self.clock = clock
+        al, bl, cl, dl, el, fl, gl, hl = gate.DMux8Way(load, address[:3])
+        return gate.Mux8Way16(
+            self.a.update(source, al, address[3: 12], clock=self.clock),
+            self.b.update(source, bl, address[3: 12], clock=self.clock),
+            self.c.update(source, cl, address[3: 12], clock=self.clock),
+            self.d.update(source, dl, address[3: 12], clock=self.clock),
+            self.e.update(source, el, address[3: 12], clock=self.clock),
+            self.f.update(source, fl, address[3: 12], clock=self.clock),
+            self.g.update(source, gl, address[3: 12], clock=self.clock),
+            self.h.update(source, hl, address[3: 12], clock=self.clock),
+            select=address[:3]
+        )
+
+
+class RAM16K(object):
+
+    def __init__(self):
+        self.a = RAM4K()
+        self.b = RAM4K()
+        self.c = RAM4K()
+        self.d = RAM4K()
+        self.clock = ClockPhase.HIGH
+
+    def update(self, source: BitArray, load: bool, address: BitArray,
+               clock: ClockPhase=None) -> BitArray:
+        if clock:
+            self.clock = clock
+        al, bl, cl, dl = gate.DMux4Way(load, address[:2])
+        return gate.Mux4Way16(
+            self.a.update(source, al, address[2: 14], clock=self.clock),
+            self.b.update(source, bl, address[2: 14], clock=self.clock),
+            self.c.update(source, cl, address[2: 14], clock=self.clock),
+            self.d.update(source, dl, address[2: 14], clock=self.clock),
+            select=address[:2]
+        )
diff --git a/test/__init__.py b/test/__init__.py
@@ -3,3 +3,9 @@
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
+
+import os
+
+
+PACKAGE_DIRECTORY = os.path.dirname(os.path.abspath(__file__))
+DATA_DIRECTORY = os.path.join(PACKAGE_DIRECTORY, 'data')