add inst_exp task.

Makefile

@@ -18,7 +18,7 @@ riscv-test:
 GTKWAVE = /Applications/gtkwave.app/Contents/Resources/bin/gtkwave
 
 view:
-	$(GTKWAVE) ./test_run_dir/simple.RiscVTester1912282511/RiscV.gtkw
+	$(GTKWAVE) ./test_run_dir/simple.RiscVTester1912282512/RiscV.gtkw
 
 # clean everything (including IntelliJ project settings)
 

inst.txt

@@ -0,0 +1,6 @@
+00000013 0 00000000 // nop
+20000093 1 00000200 // li ra, 512
+00002137 2 00002000 // lui sp, 0x2
+02008093 1 00000220 // addi ra, ra, 32
+002081b3 3 00002220 // add gp, ra, sp
+00100293 5 00000001 // li t0, 1

src/main/scala/simple/Interface.scala

@@ -16,7 +16,7 @@ class IF_IDtoRF  extends Bundle {
 class IF_IDtoEX  extends Bundle {
   val alu_func   = Output(UInt( 6.W))
   val ldst_func  = Output(UInt( 6.W))
-  val imm        = Output(UInt(12.W))
+  val imm        = Output(UInt(32.W))
   val rd         = Output(UInt( 5.W))
   val valid      = Output(UInt( 1.W))
 }

src/main/scala/simple/RiscV.scala

@@ -23,6 +23,53 @@ class ID extends Module {
     var if_IDtoRF      = new IF_IDtoRF
   })
 
+  val inst_code = Wire(UInt(32.W))
+  inst_code := io.if_IFtoID.opcode
+
+  var opcode = inst_code(6,0)
+  var rd = inst_code(11,7)
+  var func3 = inst_code(14,12)
+  var rs1 = inst_code(19,15)
+  var rs2 = inst_code(24,20)
+  var func7 = inst_code(31,25)
+  var imm_I = inst_code(31,20)
+  // var imm_S = inst_code(7,7)
+  var imm_U = inst_code(31,12)
+  // var imm_J = inst_code(31,31)
+  var shamt = inst_code(24,20)
+
+  // opcode
+  val illigal_op   = Wire(Bool())
+  val lui_valid    = Wire(Bool())
+  val load_valid   = Wire(Bool())
+  val op_imm_valid = Wire(Bool())
+  val op_valid     = Wire(Bool())
+  val store_valid  = Wire(Bool())
+  illigal_op   := 0.U
+  lui_valid    := 0.U
+  load_valid   := 0.U
+  op_imm_valid := 0.U
+  op_valid     := 0.U
+  store_valid  := 0.U
+  when(opcode===0x03.U){
+    load_valid := 1.U
+  }.elsewhen(opcode===0x13.U){
+    op_imm_valid := 1.U
+  }.elsewhen(opcode===0x33.U){
+    op_valid := 1.U
+  }.elsewhen(opcode===0x23.U){
+    store_valid := 1.U
+  }.elsewhen(opcode===0x37.U){
+    lui_valid := 1.U
+  }.otherwise{
+    illigal_op := 1.U
+  }
+  // assert(illigal_op === 0x0.U, "[NG]Illigal OP!!")
+
+  // imm sel
+  val imm = Wire(UInt(32.W))
+  imm := 0.U
+
   // Output
   io.if_IDtoEX.alu_func  := 1.U
   io.if_IDtoEX.ldst_func := 2.U

src/test/scala/simple/RiscVTester.scala

@@ -3,10 +3,23 @@ package simple
 import chisel3._
 import chisel3.iotesters.PeekPokeTester
 
+import scala.io.Source
+
 /**
  * Test the RiscV design
  */
 class RiscVTester(dut: RiscV) extends PeekPokeTester(dut) {
+  def f_run_instruction_exp(
+          inst_code : UInt,
+          reg_num   : Int,
+          exp       : Int
+    ) : Int = {
+    f_run_instruction(inst_code)
+    expect(dut.io.info_rf(reg_num), exp)
+    var reg_val = peek(dut.io.info_rf(reg_num))
+    println(f"reg_num[0x$reg_num%02x] reg_val[0x$reg_val%08x] exp[0x$exp%08x]");
+    return 0;
+  }
   def f_run_instruction(
           inst_code : UInt
     ) : Int = {
@@ -23,9 +36,23 @@ class RiscVTester(dut: RiscV) extends PeekPokeTester(dut) {
     step(1)
     return 0;
   }
+  val filename = "inst.txt"
+  for (line <- Source.fromFile(filename).getLines) {
+      println(line)
+      // println(lines(0))
+      // println(lines(1))
+      // println(lines(2))
+      var lines = line.split(" ")
+      var inst_code = lines(0)
+      var reg_num   = Integer.parseInt(lines(1), 16)
+      var expect    = Integer.parseInt(lines(2), 16)
+
+      var inst = Integer.parseInt(inst_code,16).U
+      // f_run_instruction(inst)
+      f_run_instruction_exp(inst, reg_num, expect)
+      step(1)
+  }
 
-  f_run_instruction(OBJ_OPCODE.OP_Nop)
-  step(1)
 
 }
 

tools/gen_insts.py

@@ -0,0 +1,60 @@
+import sys
+
+
+Inst_List = [] # [[ADDR, opcode, ExpectReg] , ..]
+ExpectReg = [] # [[x0, value]
+
+Start_ADDR = "0xffffffff80000000"
+state = "init"
+for line in open("../riscv_testpattern/run.log"):
+  line = line.rstrip()
+  line = line.split()
+  print state
+  print line
+  if(state=="init"):
+    ADDR   = line[2]
+    if(ADDR == Start_ADDR):
+      state = "get_inst"
+    else:
+      continue
+
+  if(state=="get_inst"):
+    if(line[0] == "core"):
+      ADDR   = line[2].replace("ffffffff800", "")
+      opcode = line[3].replace("(", "").replace(")", "")
+      asm    = " ".join(line[4:])
+      state = "get_expect"
+    else:
+      print("No expect register. jump loop or else")
+      break 
+  elif(state=="get_expect"):
+    op    = line[2]
+    if(op == "(0x00000013)"):   # NOP
+      line.append("0")
+      line.append("0")
+      line.append("0x00000000")
+    elif((op == "(0x0040006f)")   # j pc + 0x4
+      |(op == "(0x0000006f)")): # j pc + 0x4
+      state = "get_inst"
+      continue
+    elif(op=="(0x00532023)"): # Fin
+      break
+
+    reg    = line[4]
+    expect = line[5]
+    Inst_List.append([ADDR, opcode, [reg, expect], asm])
+    state = "get_inst"
+
+file = open('./inst.txt', 'w')
+
+print(Inst_List)
+for Inst in Inst_List:
+  opcode = Inst[1].replace("0x","")
+  reg    = Inst[2][0]
+  expect = Inst[2][1].replace("0x","")
+  asm    = Inst[3]
+  inst = "{0} {1} {2} // {3}\n".format(opcode, reg, expect, asm)
+  file.writelines(inst)
+  #print(inst)
+
+file.close()