mod imm for signed.

Makefile

@@ -18,8 +18,8 @@ riscv-test:
 GTKWAVE = /Applications/gtkwave.app/Contents/Resources/bin/gtkwave
 
 view:
-	# $(GTKWAVE) ./test_run_dir/simple.RiscVTester1912282512/RiscV.gtkw
-	$(GTKWAVE) ./test_run_dir/simple.RiscVTester1912282511/RiscV.gtkw
+	$(GTKWAVE) ./test_run_dir/simple.RiscVTester1912282512/RiscV.gtkw
+	# $(GTKWAVE) ./test_run_dir/simple.RiscVTester1912282511/RiscV.gtkw
 
 # clean everything (including IntelliJ project settings)
 

expect.txt

@@ -1,22 +1,22 @@
-00000013 0 00000000 80000000 80000004 // nop
-20000093 1 00000200 80000004 80000008 // li ra, 512
-80002137 2 80002000 80000008 8000000c // lui sp, 0x80002
-02008093 1 00000220 8000000c 80000010 // addi ra, ra, 32
-002081b3 3 80002220 80000010 80000014 // add gp, ra, sp
-01c000ef 1 80000018 80000014 80000030 // jal pc + 0x1c
-fe010113 2 80001fe0 80000030 80000034 // addi sp, sp, -32
-00812e23 e 80001ffc 80000034 80000038 // sw s0, 28(sp)
-02010413 8 80002000 80000038 8000003c // addi s0, sp, 32
-00100793 1 00000001 8000003c 80000040 // li a5, 1
-fef42623 e 80001fec 80000040 80000044 // sw a5, -20(s0)
-fec42783 1 00000001 80000044 80000048 // lw a5, -20(s0)
-00178793 1 00000002 80000048 8000004c // addi a5, a5, 1
-fef42423 e 80001fe8 8000004c 80000050 // sw a5, -24(s0)
-fe842783 1 00000002 80000050 80000054 // lw a5, -24(s0)
-00078513 1 00000002 80000054 80000058 // mv a0, a5
-01c12403 8 00000000 80000058 8000005c // lw s0, 28(sp)
-02010113 2 80002000 8000005c 80000060 // addi sp, sp, 32
-00008067 0 00000000 80000060 80000018 // ret
-00100293 5 00000001 80000018 8000001c // li t0, 1
-00000317 6 8000001c 8000001c 80000020 // auipc t1, 0x0
-06430313 6 80000080 80000020 0 // addi t1, t1, 100
+00000013 00 00000000 80000000 80000004 // nop
+20000093 01 00000200 80000004 80000008 // li ra, 512
+80002137 02 80002000 80000008 8000000c // lui sp, 0x80002
+02008093 01 00000220 8000000c 80000010 // addi ra, ra, 32
+002081b3 03 80002220 80000010 80000014 // add gp, ra, sp
+01c000ef 01 80000018 80000014 80000030 // jal pc + 0x1c
+fe010113 02 80001fe0 80000030 80000034 // addi sp, sp, -32
+00812e23 00 00000000 80000034 80000038 // sw s0, 28(sp)
+02010413 08 80002000 80000038 8000003c // addi s0, sp, 32
+00100793 15 00000001 8000003c 80000040 // li a5, 1
+fef42623 00 00000000 80000040 80000044 // sw a5, -20(s0)
+fec42783 15 00000001 80000044 80000048 // lw a5, -20(s0)
+00178793 15 00000002 80000048 8000004c // addi a5, a5, 1
+fef42423 00 00000000 8000004c 80000050 // sw a5, -24(s0)
+fe842783 15 00000002 80000050 80000054 // lw a5, -24(s0)
+00078513 10 00000002 80000054 80000058 // mv a0, a5
+01c12403 08 00000000 80000058 8000005c // lw s0, 28(sp)
+02010113 02 80002000 8000005c 80000060 // addi sp, sp, 32
+00008067 00 00000000 80000060 80000018 // ret
+00100293 05 00000001 80000018 8000001c // li t0, 1
+00000317 06 8000001c 8000001c 80000020 // auipc t1, 0x0
+06430313 06 80000080 80000020 0 // addi t1, t1, 100

src/main/scala/simple/ID.scala

@@ -22,7 +22,16 @@ class ID extends Module {
   var rs1 = inst_code(19,15)
   var rs2 = inst_code(24,20)
   var func7 = inst_code(31,25)
-  var imm_I = inst_code(31,20)
+  // // var imm_I = inst_code(31,20)
+  // val imm_I_SInt = Wire(SInt(12.W))
+  // imm_I_SInt := inst_code(31,20).asSInt
+  val imm_I  = Wire(UInt(32.W))
+  when(inst_code(31)===0.U){ // +
+    imm_I      := inst_code(30,20)
+  }.otherwise{
+    imm_I      := (0xFFFFF000L.U | inst_code(31,20))
+  }
+
   // var imm_S = inst_code(7,7)
   var imm_U = (inst_code(31,12) << 12)
   // var imm_J = inst_code(31,31)

src/test/scala/simple/RiscVTester.scala

@@ -18,7 +18,10 @@ class RiscVTester(dut: RiscV) extends PeekPokeTester(dut) {
     result &= f_run_instruction(inst_code)
     expect(dut.io.info_rf(reg_num), exp)
     var reg_val = peek(dut.io.info_rf(reg_num))
-    println(f"reg_num[0x$reg_num%02x] reg_val[0x$reg_val%08x] exp[0x$exp%08x]");
+    if(reg_val != exp){
+      println(f"reg_num[0x$reg_num%02x] reg_val[0x$reg_val%08x] exp[0x$exp%08x]");
+      result = 0
+    }
     return result;
   }
   def f_run_instruction(
@@ -83,14 +86,16 @@ class RiscVTester(dut: RiscV) extends PeekPokeTester(dut) {
     var EXP_ADDR  = BigInt(lines(4), 16) // Next PC
 
     // var inst      = Integer.parseInt(inst_code,16).U
-    var reg_num   = Integer.parseInt(lines(1), 16)
+    var reg_num   = Integer.parseInt(lines(1), 10)
     // var expect    = Integer.parseInt(lines(2), 16)
     // var EXP_ADDR  = Integer.parseInt(lines(3), 16) // cuurent PC
     // var EXP_ADDR  = Integer.parseInt(lines(4), 16) // Next PC
 
     // f_run_instruction(inst)
     if(f_run_instruction_exp(inst.U, reg_num, expect)!=1){
-      println("[NG] f_run_instruction_exp")
+      println(f"[NG] f_run_instruction_exp")
+      println(f"[NG] ADDR[0x$inst_addr%08x]: CODE[0x$inst%08x]")
+       println("[NG] ERROR LINE: "+line)
       timer = TIME_MAX
     }
     step(1)

tools/gen_expect.py

@@ -9,15 +9,14 @@
 for line in open("../riscv_testpattern/run.log"):
   line = line.rstrip()
   line = line.split()
-  print state
-  print line
+  # print state
+  # print line
   if(state=="init"):
     ADDR   = line[2]
     if(ADDR == Start_ADDR):
       state = "get_inst"
     else:
       continue
-
   if(state=="get_inst"):
     if(line[0] == "core"):
       ADDR   = line[2].replace("ffffffff", "")
@@ -35,7 +34,8 @@
       line.append("0x00000000")
     elif((op == "(0x0040006f)") # j pc + 0x4
       |(op == "(0x00008067)")   #  ret
-      |(op == "(0x0000006f)")): # j pc + 0x0
+      |(op == "(0x0000006f)")   # j pc + 0x0
+      ): 
       # state = "get_inst"
       # continue
       line.append("0")
@@ -45,18 +45,21 @@
       break
 
     regx = line[3]
-    if(len(regx)==3): # x10,x11..
-      reg    = regx[1:2]
+    if (op[9:12] == "23)"):# sw(0x13)
+      reg    = "00"
+      expect = "0x00000000"
+    elif(len(regx)==3): # x10,x11..
+      reg    = regx[1:3]
       expect = line[4]
     else: # x 1, 
-      reg    = line[4]
+      reg    = "0"+line[4]
       expect = line[5]
     Inst_List.append([ADDR, opcode, [reg, expect], asm])
     state = "get_inst"
 
 file = open('./expect.txt', 'w')
 
-print(Inst_List)
+# print(Inst_List)
 for i in range(len(Inst_List)):
   Inst = Inst_List[i]
   opcode    = Inst[1].replace("0x","")