mod Top for timing met.

moamoai · Mar 10, 2020 · b5e8fcc · b5e8fcc
1 parent c6aaa68
commit b5e8fcc
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Showing 3 changed files with 16 additions and 59 deletions.
diff --git a/src/main/scala/top/Top.scala b/src/main/scala/top/Top.scala
@@ -9,24 +9,25 @@ package top
 import chisel3._
 import chisel3.util._
 import uart.Uart
-// import uart.Memory
-// import riscv.Memory_BD
-//import riscv.Memory
 import riscv.RiscV
 
-/**
- * A simple, configurable counter that wraps around.
- */
-class Top(TIME_BAUD:UInt = 1085.U(16.W)) extends Module {
+import multiclock.Divider
+
+// class Top(TIME_BAUD:UInt = 1085.U(16.W)) extends Module { // 125MHz/115200bps
+class Top(TIME_BAUD:UInt = 542.U(16.W)) extends Module {
   val io = IO(new Bundle {
     val SW_IN  = Input(UInt(4.W))
     val RD     = Input(UInt(1.W))
     val TD     = Output(UInt(1.W))
     val GPIO   = Output(UInt(8.W))
   })
 
+  val clk_div2 = Wire(Clock())
+  val i_div2 = Module(new Divider)
+  clk_div2 := i_div2.io.clock
+
+withClock (clk_div2) {
   val i_uart = Module(new Uart(TIME_BAUD, 32, 32))
-  // val i_uart = Module(new Uart(TIME_BAUD, 8, 8))
   i_uart.io.RD := io.RD
   io.TD        := i_uart.io.TD
 
@@ -38,24 +39,8 @@ class Top(TIME_BAUD:UInt = 1085.U(16.W)) extends Module {
   i_rv_ifm.io.pre_inst_valid := i_uart.io.GPIO(0)(2)
   i_rv_ifm.io.GPIO_1         := i_uart.io.GPIO(1)
 
-//  val pre_start    = Wire   (UInt(1.W))
-//  val start        = Wire   (UInt(1.W))
-//  val r_start      = RegInit(0.U(1.W))
-//  val pre_inst_valid = Wire   (UInt(1.W))
-//  val inst_valid     = Wire   (UInt(1.W))
-//  val r_inst_valid   = RegInit(0.U(1.W))
-//  pre_start      := i_uart.io.GPIO(0)(1) // 0.U
-//  r_start        := pre_start
-//  pre_inst_valid := i_uart.io.GPIO(0)(2) // 0.U
-//  r_inst_valid   := pre_inst_valid
-//
-//  start      := pre_start      & (r_start === 0.U)      // pulse
-//  inst_valid := pre_inst_valid & (r_inst_valid === 0.U) // pulse
-
   val i_riscv  = Module(new RiscV)
   i_riscv.io.if_mem_bd.bd_en := i_uart.io.GPIO(0)(0) // 1.U
-  //i_riscv.io.start           := start
-  //i_riscv.io.inst_valid      := inst_valid
   i_riscv.io.start           := i_rv_ifm.io.start
   i_riscv.io.inst_valid      := i_rv_ifm.io.inst_valid
   i_uart.io.rdata            := i_riscv.io.if_mem_bd.rdata
@@ -68,43 +53,11 @@ class Top(TIME_BAUD:UInt = 1085.U(16.W)) extends Module {
   i_rv_ifm.io.error      := i_riscv.io.error
   i_rv_ifm.io.info_rf    := i_riscv.io.info_rf
 
-//  // Monitor
-//  val reg_sel   = Wire(UInt(5.W))
-//  val reg_rstrb = Wire(UInt(2.W))
-//  reg_sel   := i_uart.io.GPIO(1)(4,0)
-//  reg_rstrb := i_uart.io.GPIO(1)(6,5)
-//  val reg_data  = Wire(UInt(8.W))
-//  reg_data := 0.U
-//  when(reg_rstrb === 0.U){
-//    reg_data := i_riscv.io.info_rf(reg_sel)(7,0)
-//  }.elsewhen(reg_rstrb === 1.U){
-//    reg_data := i_riscv.io.info_rf(reg_sel)(15,8)
-//  }.elsewhen(reg_rstrb === 2.U){
-//    reg_data := i_riscv.io.info_rf(reg_sel)(23,16)
-//  }.elsewhen(reg_rstrb === 3.U){
-//    reg_data := i_riscv.io.info_rf(reg_sel)(31,24)
-//  }
-//
-//  val r_error      = RegInit(0.U(1.W))
-//  val r_inst_ready = RegInit(0.U(1.W))
-//  when(i_riscv.io.error === 1.U){
-//    r_error := 1.U
-//  }.elsewhen(inst_valid === 1.U){
-//    r_error := 0.U
-//  }
-//  when(i_riscv.io.inst_ready === 1.U){
-//    r_inst_ready := 1.U
-//  }.elsewhen(inst_valid === 1.U){
-//    r_inst_ready := 0.U
-//  }
-//
-//  i_uart.io.MONITOR(1) := Cat(r_error, r_inst_ready)
-//  i_uart.io.MONITOR(2) := i_riscv.io.inst_addr
-//  i_uart.io.MONITOR(3) := reg_data
   i_uart.io.MONITOR(1) := i_rv_ifm.io.MONITOR_1
   i_uart.io.MONITOR(2) := i_rv_ifm.io.MONITOR_2
   i_uart.io.MONITOR(3) := i_rv_ifm.io.MONITOR_3
 }
+}
 
 object TopMain extends App {
   println("Generating the Top hardware")

diff --git a/src/test/scala/top/TopTester.scala b/src/test/scala/top/TopTester.scala
@@ -9,7 +9,9 @@ import chisel3._
 import chisel3.iotesters.PeekPokeTester
 
 object OBJ_TEST {
-  val TIME_BAUD  = 16
+  val TIME_BAUD      = 32
+  val TIME_BAUD_Top  = 16
+  //val TIME_BAUD  = 16
 }
 
 /**
@@ -179,7 +181,7 @@ object TopTester extends App {
 
   iotesters.Driver.execute(Array[String]("--generate-vcd-output", "on",
                         "--fint-write-vcd", "--wave-form-file-name", "test_run_dir/Top.vcd"),
-                        () => new Top(OBJ_TEST.TIME_BAUD.U)) {
+                        () => new Top(OBJ_TEST.TIME_BAUD_Top.U)) {
     dut => new TopTester(dut)
   }
 }
diff --git a/vivado/top.xdc b/vivado/top.xdc
@@ -33,3 +33,5 @@ set_property IOSTANDARD LVCMOS33 [get_ports {io_GPIO[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {io_GPIO[0]}]
 
 create_clock -period 8.000 -name clock -waveform {0.000 4.000} [get_ports clock]
+
+create_generated_clock -name clk_div2 -source [get_ports clock] -divide_by 2 [get_pins i_div2/r_clock_reg/Q]