Add STM32C0x

.github/workflows/linux.yml

@@ -183,6 +183,10 @@ jobs:
         if: always()
         run: |
           (cd examples && ../tools/scripts/examples_compile.py nucleo_h743zi nucleo_h723zg stm32h750vbt6_devebox)
+      - name: Examples STM32C0 Series
+        if: always()
+        run: |
+          (cd examples && ../tools/scripts/examples_compile.py stm32c0x)
 
   stm32f4-examples-1:
     runs-on: ubuntu-22.04

examples/stm32c0x/blink/main.cpp

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2024, Jörg Ebeling
+ *
+ * This file is part of the modm project.
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/.
+ */
+
+#include <modm/platform.hpp>
+
+using namespace modm::platform;
+using namespace std::chrono_literals;
+
+using Led = GpioC14;
+
+int
+main()
+{
+	Led::setOutput();
+	while (true)
+	{
+		Led::toggle();
+		modm::delay(0.5s);
+	}
+}

examples/stm32c0x/blink/project.xml

@@ -0,0 +1,18 @@
+<library>
+  <repositories>
+    <repository>
+      <path>../../../repo.lb</path>
+    </repository>
+  </repositories>
+  <options>
+    <option name="modm:target">stm32c011f6p6</option>
+    <option name="modm:build:build.path">../../../build/stm32c0x/blink</option>
+  </options>
+  <modules>
+    <module>modm:platform:core</module>
+    <module>modm:platform:rcc</module>
+    <module>modm:platform:gpio</module>
+    <module>modm:architecture:delay</module>
+    <module>modm:build:scons</module>
+  </modules>
+</library>

ext/st/module.lb

@@ -127,7 +127,7 @@ def common_header_file(env):
     define = None
 
     content = Path(localpath(folder, family_header)).read_text(encoding="utf-8", errors="replace")
-    match = re.findall(r"if defined\((?P<define>STM32[FGHLU][\w\d]+)\)", content)
+    match = re.findall(r"if defined\((?P<define>STM32[CFGHLU][\w\d]+)\)", content)
     define = getDefineForDevice(device.identifier, match)
     if define is None or match is None:
         raise ValidateException("No device define found for '{}'!".format(device.partname))

repo.lb

@@ -83,7 +83,8 @@ class DevicesCache(dict):
         device_file_names += glob.glob(repopath("tools/devices/**/*.xml"))
 
         # roughly filter to supported devices
-        supported = ["stm32f0", "stm32f1", "stm32f2", "stm32f3", "stm32f4", "stm32f7",
+        supported = ["stm32c0",
+                     "stm32f0", "stm32f1", "stm32f2", "stm32f3", "stm32f4", "stm32f7",
                      "stm32g0", "stm32g4",
                      "stm32h7",
                      "stm32l0", "stm32l1", "stm32l4", "stm32l5",

src/modm/platform/clock/stm32/module.lb

@@ -65,13 +65,14 @@ def build(env):
     properties["pllprediv2"] = False    # FIXME: not sure what value this should have
     properties["pll_hse_prediv2"] = target["family"] == "f1" and target["name"] in ["01", "02", "03"]
     properties["hsi48"] = \
+        (target["family"] == "c0") or \
         (target["family"] == "f0" and target["name"] in ["42", "48", "71", "72", "78", "91", "98"]) or \
         (target["family"] == "l4" and target["name"][0] not in ["7", "8"]) or \
         (target["family"] == "l5") or \
         (target["family"] == "u5")
     if target["family"] in ["l4", "l5"]:
         properties["hsi48_cr"] = "CRRCR"
-    elif target["family"] in ["u5"]:
+    elif target["family"] in ["c0", "u5"]:
         properties["hsi48_cr"] = "CR"
     else:
         properties["hsi48_cr"] = "CR2"
@@ -111,8 +112,8 @@ def build(env):
                         if target.family == "h7" else ""
     properties["cfgr3"] = ("SRDCFGR" if target.name in ["a0", "a3", "b0", "b3"] else "D3CFGR")
     properties["d3"] = ("SRD" if target.name in ["a0", "a3", "b0", "b3"] else "D3")
-    properties["bdcr"] = "CSR" if target.family in ["l0", "l1"] else "BDCR"
-    properties["pll_ids"] = ["1", "2", "3"] if target.family in ["h7", "u5"] else [""]
+    properties["bdcr"] = "CSR1" if target.family in ["c0"] else "CSR" if target.family in ["l0", "l1"] else "BDCR"
+    properties["pll_ids"] = ["1", "2", "3"] if target.family in ["h7", "u5"] else [] if target.family in ["c0"] else [""]
     properties["has_smps"] = target["family"] == "h7" and (target["name"] in ["25", "35", "45", "47", "55", "57"] or \
         (target["name"] in ["30", "a3", "b0", "b3"] and target["variant"] == "q"))
     properties["ccipr1"] = "CCIPR1" if target.family in ["l5", "u5"] else "CCIPR"

src/modm/platform/clock/stm32/rcc.cpp.in

@@ -40,12 +40,13 @@ Rcc::enableInternalClockMHz14(uint32_t waitCycles)
 %% endif
 
 %% if hsi48
+%% set hsi_name="HSI" if target.family in ["c0"] else "HSI48"
 bool
 Rcc::enableInternalClockMHz48(uint32_t waitCycles)
 {
 	bool retval;
-	RCC->{{hsi48_cr}} |= RCC_{{hsi48_cr}}_HSI48ON;
-	while (not (retval = (RCC->{{hsi48_cr}} & RCC_{{hsi48_cr}}_HSI48RDY)) and --waitCycles)
+	RCC->{{hsi48_cr}} |= RCC_{{hsi48_cr}}_{{hsi_name}}ON;
+	while (not (retval = (RCC->{{hsi48_cr}} & RCC_{{hsi48_cr}}_{{hsi_name}}RDY)) and --waitCycles)
 		;
 	return retval;
 }
@@ -125,7 +126,7 @@ Rcc::enableExternalCrystal(uint32_t waitCycles)
 }
 
 
-%% set lsi_cr="BDCR" if target.family in ["u5"] else "CSR"
+%% set lsi_cr="CSR2" if target.family in ["c0"] else "BDCR" if target.family in ["u5"] else "CSR"
 bool
 Rcc::enableLowSpeedInternalClock(uint32_t waitCycles)
 {

src/modm/platform/clock/stm32/rcc.hpp.in

@@ -102,10 +102,16 @@ public:
 		Hsi16 = 0b10,
 		Hse = 0b11,
 %% endif
-%% if hsi48 and target.family not in ["l4", "l5", "u5"]
-		/// High speed internal clock (48 MHz)
+%% if hsi48 
+	/// High speed internal clock (48 MHz)
+	%% if target.family in ["c0"]
+		Hsi48 = RCC_CFGR_SWS_HSI,
+		InternalClockMHz48 = Hsi48,
+		Hse = RCC_CFGR_SWS_HSE,
+	%% elif target.family not in ["l4", "l5", "u5"]
 		Hsi48 = RCC_CFGR_PLLSRC_HSI48_PREDIV,
 		InternalClockMHz48 = Hsi48,
+	%% endif
 %% endif
 %% if target.family in ["l4"]
 		Msi = RCC_PLLCFGR_PLLSRC_MSI,
@@ -134,7 +140,9 @@ public:
 	enum class
 	SystemClockSource : uint32_t
 	{
-%% if target.family == "l5"
+%% if target.family == "c0"
+		Hsi = RCC_CFGR_SWS_HSI,
+%% elif target.family == "l5"
 		Msi = 0,
 		Hsi = RCC_CFGR_SW_0,
 		Hsi16 = Hsi,
@@ -194,7 +202,7 @@ public:
 	enum class
 	AhbPrescaler : uint32_t
 	{
-%% if target.family in ["l5", "u5"]
+%% if target.family in ["c0", "l5", "u5"]
 		Div1   = 0b0000 << RCC_{{cfgr_prescaler}}_HPRE_Pos,
 		Div2   = 0b1000 << RCC_{{cfgr_prescaler}}_HPRE_Pos,
 		Div4   = 0b1001 << RCC_{{cfgr_prescaler}}_HPRE_Pos,
@@ -217,7 +225,17 @@ public:
 %% endif
 	};
 
-%% if target.family in ["f0", "g0"]
+%% if target.family in ["c0"]
+	enum class
+	ApbPrescaler : uint32_t
+	{
+		Div1   = RCC_CFGR_PPRE_0,
+		Div2   = RCC_CFGR_PPRE_2,
+		Div4   = RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0,
+		Div8   = RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1,
+		Div16  = RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0
+	};
+%% elif target.family in ["f0", "g0"]
 	enum class
 	ApbPrescaler : uint32_t
 	{
@@ -396,7 +414,7 @@ public:
 		Csi = RCC_CFGR_MCO2_2,
 		Lsi = RCC_CFGR_MCO2_2 | RCC_CFGR_MCO2_0
 	};
-%% elif target.family in ["l0", "l1", "l4", "l5", "g0", "g4", "u5"]
+%% elif target.family in ["l0", "l1", "l4", "l5", "g0", "g4", "u5", "c0"]
 %% set cfgr_mco="CFGR1" if target.family in ["u5"] else "CFGR"
 	enum class
 	ClockOutputSource : uint32_t
@@ -835,7 +853,7 @@ public:
 		RCC->CFGR = tmp | uint32_t(src);
 		return true;
 	}
-%% elif target.family in ["l0", "l1", "l4", "l5", "g0", "g4", "u5"]
+%% elif target.family in ["l0", "l1", "l4", "l5", "g0", "g4", "u5", "c0"]
 	enum class
 	ClockOutputPrescaler : uint32_t
 	{
@@ -844,7 +862,7 @@ public:
 		Div4 = (2 << RCC_{{cfgr_mco}}_MCOPRE_Pos),
 		Div8 = (3 << RCC_{{cfgr_mco}}_MCOPRE_Pos),
 		Div16 = (4 << RCC_{{cfgr_mco}}_MCOPRE_Pos),
-%% if target.family in ["g0"]
+%% if target.family in ["c0", "g0"]
 		Div32 = (5 << RCC_{{cfgr_mco}}_MCOPRE_Pos),
 		Div64 = (6 << RCC_{{cfgr_mco}}_MCOPRE_Pos),
 		Div128 = (7 << RCC_{{cfgr_mco}}_MCOPRE_Pos),
@@ -874,7 +892,7 @@ public:
 		return true;
 	}
 
-%% if target.family in ["f0", "g0"]
+%% if target.family in ["c0", "f0", "g0"]
 	static inline bool
 	setApbPrescaler(ApbPrescaler prescaler)
 	{

src/modm/platform/clock/stm32/rcc_impl.hpp.in

@@ -63,7 +63,7 @@ Rcc::setFlashLatency()
 %% if target["family"] in ["f2", "f4", "l4", "g4"]
 	// enable flash prefetch and data and instruction cache
 	acr |= FLASH_ACR_PRFTEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN;
-%% elif target["family"] in ["g0"]
+%% elif target["family"] in ["c0", "g0"]
 	// enable flash prefetch and instruction cache
 	acr |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN;
 %% elif target["family"] == "f7"

src/modm/platform/core/stm32/module.lb

@@ -57,6 +57,7 @@ def build(env):
     # (cycles per loop, setup cost in loops)
     tuning = {
         "g4": (3,  4), # CM4  tested on G476 in RAM
+        "c0": (3,  4), # CM0+ TODO: Test
         "l0": (3,  4), # CM0+ tested on L031 in RAM
         "g0": (3,  4), # CM0+ tested on G072 in RAM
         "f7": (4,  4), # CM7  tested on F767 in ITCM

src/modm/platform/core/stm32/startup_platform.c.in

@@ -29,7 +29,7 @@ void
 __modm_initialize_platform(void)
 {
 	// Enable SYSCFG
-%% if target.family == "g0"
+%% if target.family in ["c0", "g0"]
 	RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN;
 %% elif target.family == "f1"
 	RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;

src/modm/platform/gpio/stm32/enable.cpp.in

@@ -28,7 +28,7 @@ modm_gpio_enable(void)
 %%	set prefix = "IOP"
 %% elif target.family in ["l4", "l5", "g4", "u5"]
 %%  set clock_tree = 'AHB2'
-%% elif target.family in ["g0", "l0"]
+%% elif target.family in ["c0", "g0", "l0"]
 %%  set clock_tree = 'IOP'
 %% endif
 

src/modm/platform/gpio/stm32/module.lb

@@ -125,6 +125,10 @@ def validate_alternate_functions(driver, env):
 def get_remap_command(family, key):
     reg = 'SYSCFG->CFGR1'
     mask = {
+        ('c0', 'a9') : 'SYSCFG_CFGR1_PA11_RMP',
+        ('c0', 'a10'): 'SYSCFG_CFGR1_PA12_RMP',
+        ('c0', 'a11'): 'SYSCFG_CFGR1_PA11_RMP',
+        ('c0', 'a12'): 'SYSCFG_CFGR1_PA12_RMP',
         ('f0', 'a9') : 'SYSCFG_CFGR1_PA11_PA12_RMP',
         ('f0', 'a10'): 'SYSCFG_CFGR1_PA11_PA12_RMP',
         ('f0', 'a11'): 'SYSCFG_CFGR1_PA11_PA12_RMP',
@@ -163,8 +167,7 @@ def prepare(module, options):
     module.depends(
         ":architecture:gpio",
         ":cmsis:device",
-        ":math:utils",
-        ":platform:rcc")
+        ":math:utils")
 
     module.add_query(EnvironmentQuery(name="all_signals", factory=lambda env: bprops["all_signals"]))
 

tools/build_script_generator/module.lb

@@ -248,7 +248,7 @@ def post_build(env):
         env.substitutions["openocd_sources"] = env.collector_values("openocd.source")
 
         linkerscript = env.query(":platform:cortex-m:linkerscript", {})
-        all_rams = [m for m in linkerscript.get("memories") if "w" in m["access"]]
+        all_rams = [m for m in linkerscript.get("memories", []) if "w" in m["access"]]
         env.substitutions["all_rams"] = all_rams
         vector_table = env.query(":platform:cortex-m:vector_table", {"vector_table_size": 16*4})
         env.substitutions["vector_table_size"] = vector_table["vector_table_size"]