Digital Logic Design
in this repository you can find Digital Logic Design projects with Modelsim and also Quartus
there is a folder for gate level design in Modelsim where you can understand the Transistor Level of Computer Architecture
the Transister level time delay is mostly (3,4,5)
Most of the projects are simulated by both Modelsim and Quartus to implement the delay times of Altra hardwares
Post Synthesis results are available in the related folder
Before simulating the .vo file don't forget to add Modelsim libraries
{altera_ver , cycloneiv_ver}