Skip to content
View mohamadahmad's full-sized avatar
Block or Report

Block or report mohamadahmad

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. dpll dpll Public

    Forked from ZipCPU/dpll

    A collection of phase locked loop (PLL) related projects

    Verilog 1

  2. covid19_inference_forecast covid19_inference_forecast Public

    Forked from Priesemann-Group/covid19_inference_forecast

    Jupyter Notebook 1

  3. aib-phy-hardware aib-phy-hardware Public

    Forked from intel/aib-phy-hardware

    Verilog

  4. RISCV_CPU RISCV_CPU Public

    Forked from Michaelvll/RISCV_CPU

    A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

    C

  5. e200_opensource e200_opensource Public

    Forked from SI-RISCV/e200_opensource

    The Ultra-Low Power RISC Core

    Verilog

  6. C4-PlantUML C4-PlantUML Public

    Forked from plantuml-stdlib/C4-PlantUML

    C4-PlantUML combines the benefits of PlantUML and the C4 model for providing a simple way of describing and communicate software architectures