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Variations in the instructions executed step by step or executed all once #31
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I really appreciate your work regarding open source RISC V simulator, RIPES, but unfortunately, an issued is encountered that is to be addressed. The step by step execution of the 'shifts' example shows variation compared to the program when run all at once. Shift Example when run all at onceShift Example with step by step executionThis issue is not only specific to this particular example, rather applies on all other examples as well. For some help, you might check the pipeline chart in both of the cases.This issue arised with the latest continuous release, on 30th Mar, 2019. I had the previous version, and that showed same number of cycle counts and instruction executed for both of the scenarios. I hope to get that fixed. |
Kindly, check this issue as well. Thank you |
Run execution would not check for ecall::exit within the pipeline, and thus would only stop when there were no more instructions to fetch and execute. While execution is correct, this results in a bug where a discrepancy between the cycles and instructions executed between stepping through the program and running through the program, were different.
Let me know what you think! 👍 |
Great work, bro. I wanted to know one thing, and after this, I would close this issue. Is Data Forwarding/bypassing technique applied already in the architecture? |
Yes, most of the multiplexers you see in the processor view are related to forwarding. |
Ok, Thank you. |
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