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Minor fixes, as requested in PR review
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@westernmagic
westernmagic committed May 24, 2020
1 parent d77f73e commit baa801a
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Showing 4 changed files with 80 additions and 76 deletions.
4 changes: 0 additions & 4 deletions src/librustc_codegen_llvm/asm.rs
View file
Expand Up @@ -414,8 +414,6 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass) -> String {
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::freg32) => "f",
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::freg64) => "d",
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => "f",
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r",
Expand Down Expand Up @@ -512,8 +510,6 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::freg32) => cx.type_f32(),
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::freg64) => cx.type_f64(),
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
Expand Down
28 changes: 24 additions & 4 deletions src/librustc_target/asm/mod.rs
View file
Expand Up @@ -52,6 +52,30 @@ macro_rules! def_reg_class {

#[macro_use]
macro_rules! def_regs {
($arch:ident $arch_reg:ident $arch_regclass:ident {}) => {
#[allow(unreachable_code)]
#[derive(Copy, Clone, RustcEncodable, RustcDecodable, Debug, Eq, PartialEq, Hash, HashStable_Generic)]
pub enum $arch_reg {}

impl $arch_reg {
pub fn parse(
_arch: super::InlineAsmArch,
mut _has_feature: impl FnMut(&str) -> bool,
_name: &str,
) -> Result<Self, &'static str> {
Err("unknown register")
}
}

pub(super) fn fill_reg_map(
_arch: super::InlineAsmArch,
mut _has_feature: impl FnMut(&str) -> bool,
_map: &mut rustc_data_structures::fx::FxHashMap<
super::InlineAsmRegClass,
rustc_data_structures::fx::FxHashSet<super::InlineAsmReg>,
>,
) {}
};
($arch:ident $arch_reg:ident $arch_regclass:ident {
$(
$reg:ident: $class:ident $(, $extra_class:ident)* = [$reg_name:literal $(, $alias:literal)*] $(% $filter:ident)?,
Expand Down Expand Up @@ -210,7 +234,6 @@ impl InlineAsmReg {
Self::Arm(r) => r.name(),
Self::AArch64(r) => r.name(),
Self::RiscV(r) => r.name(),
Self::Nvptx(r) => r.name(),
}
}

Expand All @@ -220,7 +243,6 @@ impl InlineAsmReg {
Self::Arm(r) => InlineAsmRegClass::Arm(r.reg_class()),
Self::AArch64(r) => InlineAsmRegClass::AArch64(r.reg_class()),
Self::RiscV(r) => InlineAsmRegClass::RiscV(r.reg_class()),
Self::Nvptx(r) => InlineAsmRegClass::Nvptx(r.reg_class()),
}
}

Expand Down Expand Up @@ -262,7 +284,6 @@ impl InlineAsmReg {
Self::Arm(r) => r.emit(out, arch, modifier),
Self::AArch64(r) => r.emit(out, arch, modifier),
Self::RiscV(r) => r.emit(out, arch, modifier),
Self::Nvptx(r) => r.emit(out, arch, modifier),
}
}

Expand All @@ -272,7 +293,6 @@ impl InlineAsmReg {
Self::Arm(r) => r.overlapping_regs(|r| cb(Self::Arm(r))),
Self::AArch64(_) => cb(self),
Self::RiscV(_) => cb(self),
Self::Nvptx(_) => cb(self),
}
}
}
Expand Down
49 changes: 3 additions & 46 deletions src/librustc_target/asm/nvptx.rs
View file
@@ -1,14 +1,11 @@
use super::{InlineAsmArch, InlineAsmType};
use rustc_macros::HashStable_Generic;
use std::fmt;

def_reg_class! {
Nvptx NvptxInlineAsmRegClass {
reg16,
reg32,
reg64,
freg32,
freg64,
}
}

Expand Down Expand Up @@ -39,52 +36,12 @@ impl NvptxInlineAsmRegClass {
) -> &'static [(InlineAsmType, Option<&'static str>)] {
match self {
Self::reg16 => types! { _: I8, I16; },
Self::reg32 => types! { _: I8, I16, I32; },
Self::reg64 => types! { _: I8, I16, I32, I64; },
Self::freg32 => types! { _: F32; },
Self::freg64 => types! { _: F32, F64; },
Self::reg32 => types! { _: I8, I16, I32, F32; },
Self::reg64 => types! { _: I8, I16, I32, F32, I64, F64; },
}
}
}

def_regs! {
Nvptx NvptxInlineAsmReg NvptxInlineAsmRegClass {
// We have to define a register, otherwise we get warnings/errors about unused imports and
// unreachable code. Do what clang does and define r0.
r0: reg32 = ["r0"],
#error = ["tid", "tid.x", "tid.y", "tid.z"] => "tid not supported for inline asm",
#error = ["ntid", "ntid.x", "ntid.y", "ntid.z"] => "ntid not supported for inline asm",
#error = ["laneid"] => "laneid not supported for inline asm",
#error = ["warpid"] => "warpid not supported for inline asm",
#error = ["nwarpid"] => "nwarpid not supported for inline asm",
#error = ["ctaid", "ctaid.x", "ctaid.y", "ctaid.z"] => "ctaid not supported for inline asm",
#error = ["nctaid", "nctaid.x", "nctaid.y", "nctaid.z"] => "nctaid not supported for inline asm",
#error = ["smid"] => "smid not supported for inline asm",
#error = ["nsmid"] => "nsmid not supported for inline asm",
#error = ["gridid"] => "gridid not supported for inline asm",
#error = ["lanemask_eq"] => "lanemask_eq not supported for inline asm",
#error = ["lanemask_le"] => "lanemask_le not supported for inline asm",
#error = ["lanemask_lt"] => "lanemask_lt not supported for inline asm",
#error = ["lanemask_ge"] => "lanemask_ge not supported for inline asm",
#error = ["lanemask_gt"] => "lanemask_gt not supported for inline asm",
#error = ["clock", "clock_hi"] => "clock not supported for inline asm",
#error = ["clock64"] => "clock64 not supported for inline asm",
#error = ["pm0", "pm1", "pm2", "pm3", "pm4", "pm5", "pm6", "pm7"] => "pm not supported for inline asm",
#error = ["pm0_64", "pm1_64", "pm2_64", "pm3_64", "pm4_64", "pm5_64", "pm6_64", "pm7_64"] => "pm_64 not supported for inline asm",
#error = ["envreg0", "envreg1", "envreg2", "envreg3", "envreg4", "envreg5", "envreg6", "envreg7", "envreg8", "envreg9", "envreg10", "envreg11", "envreg12", "envreg13", "envreg14", "envreg15", "envreg16", "envreg17", "envreg18", "envreg19", "envreg20", "envreg21", "envreg22", "envreg23", "envreg24", "envreg25", "envreg26", "envreg27", "envreg28", "envreg29", "envreg30", "envreg31"] => "envreg not supported for inline asm",
#error = ["globaltimer", "globaltimer_lo", "globaltimer_hi"] => "globaltimer not supported for inline asm",
#error = ["total_mem_size"] => "total_mem_size not supported for inline asm",
#error = ["dynamic_mem_size"] => "dynamic_mem_size not supported for inline asm",
}
}

impl NvptxInlineAsmReg {
pub fn emit(
self,
out: &mut dyn fmt::Write,
_arch: InlineAsmArch,
_modifier: Option<char>,
) -> fmt::Result {
out.write_str(self.name())
}
Nvptx NvptxInlineAsmReg NvptxInlineAsmRegClass {}
}
75 changes: 53 additions & 22 deletions src/test/assembly/asm/nvptx-types.rs
View file
@@ -1,6 +1,7 @@
// no-system-llvm
// assembly-output: emit-asm
// compile-flags: --target --nvptx64-nvidia-cuda
// compile-flags: -Z merge-functions=disabled
// only-nvptx64
// ignore-nvptx64

Expand Down Expand Up @@ -53,57 +54,87 @@ macro_rules! check {
($func:ident $ty:ident, $class:ident $mov:literal) => {
#[no_mangle]
pub unsafe fn $func(x: $ty) -> $ty {
// Hack to avoid function merging
extern "Rust" {
fn dont_merge(s: &str);
}
dont_merge(stringify!($func));

let y;
asm!(concat!($mov, " {}, {};"), out($class) y, in($class) x);
y
}
};
}

// CHECK-LABEL: reg_i8
// CHECK-LABEL: reg16_i8
// CHECK: #APP
// CHECK: mov.i16 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg_i8 i8 reg16 "mov.i16");
check!(reg16_i8 i8 reg16 "mov.i16");

// CHECK-LABEL: reg_i16
// CHECK-LABEL: reg16_i16
// CHECK: #APP
// CHECK: mov.i16 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg_i16 i16 reg16 "mov.i16");
check!(reg16_i16 i16 reg16 "mov.i16");

// CHECK-LABEL: reg32_i8
// CHECK: #APP
// CHECK: mov.i32 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg32_i8 i8 reg32 "mov.i32");

// CHECK-LABEL: reg32_i16
// CHECK: #APP
// CHECK: mov.i32 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg32_i16 i16 reg32 "mov.i32");

// CHECK-LABEL: reg_i32
// CHECK-LABEL: reg32_i32
// CHECK: #APP
// CHECK: mov.i32 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg_i32 i32 reg32 "mov.i32");
check!(reg32_i32 i32 reg32 "mov.i32");

// CHECK-LABEL: reg_f32
// CHECK-LABEL: reg32_f32
// CHECK: #APP
// CHECK: mov.f32 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: mov.i32 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg32_f32 f32 reg32 "mov.i32");

// CHECK-LABEL: reg64_i8
// CHECK: #APP
// CHECK: mov.i64 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg_f32 f32 freg32 "mov.f32");
check!(reg64_i8 i8 reg64 "mov.i64");

// CHECK-LABEL: reg_i54
// CHECK-LABEL: reg64_i16
// CHECK: #APP
// CHECK: mov.i64 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg_i64 i64 reg64 "mov.i64");
check!(reg64_i16 i16 reg64 "mov.i64");

// CHECK-LABEL: reg_f64
// CHECK-LABEL: reg64_i32
// CHECK: #APP
// CHECK: mov.f64 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: mov.i64 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg64_i32 i32 reg64 "mov.i64");

// CHECK-LABEL: reg64_f32
// CHECK: #APP
// CHECK: mov.i64 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg64_f32 f32 reg64 "mov.i64");

// CHECK-LABEL: reg64_i64
// CHECK: #APP
// CHECK: mov.i64 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg64_i64 i64 reg64 "mov.i64");

// CHECK-LABEL: reg64_f64
// CHECK: #APP
// CHECK: mov.i64 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg_f64 f64 freg64 "mov.f64");
check!(reg64_f64 f64 reg64 "mov.i64");

// CHECK-LABEL: reg_ptr
// CHECK-LABEL: reg64_ptr
// CHECK: #APP
// CHECK: mov.i64 {{[a-z0-9]+}}, {{[a-z0-9]+}};
// CHECK: #NO_APP
check!(reg_ptr ptr reg64 "mov.i64");
check!(reg64_ptr ptr reg64 "mov.i64");

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