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Popular repositories

  1. OpenTitan project repository

    SystemVerilog 1

  2. Forked from pulp-platform/uvm-components

    Contains commonly used UVM components (agents, environments and tests).

    SystemVerilog

  3. Forked from pulp-platform/axi_node

    AXI X-Bar

    SystemVerilog

  4. Forked from PrincetonUniversity/openpiton

    The OpenPiton Platform

    Assembly 1

  5. Forked from pulp-platform/common_cells

    Common SV components

    SystemVerilog

  6. Forked from pulp-platform/fpga-support

    IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs

    SystemVerilog

776 contributions in the last year

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Activity overview
Contributed to lowRISC/opentitan, pulp-platform/ariane, PrincetonUniversity/openpiton and 5 other repositories
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Contribution activity

November 2019

Created a pull request in lowRISC/opentitan that received 9 comments

[rv_plic] Implement a binary tree variant of the rv_plic_target module

Carried over from #624. This implements a solution that uses a binary tree to gather the interrupts and forward the highest priority request. As su…

+91 −145 9 comments

Created an issue in lowRISC/opentitan that received 12 comments

[lint] Demote lint error for default branches in full case statements

Our current lint rule deck treats default: branches in full case statement as lint errors. For example, the below snippet would throw an error: o…

12 comments

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