Func: implement Chapter5_1

lib/Target/Cpu0/Cpu0MCInstLower.h

@@ -12,6 +12,7 @@
 
 #include "Cpu0Config.h"
 
+#include "MCTargetDesc/Cpu0MCExpr.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/Support/Compiler.h"

lib/Target/Cpu0/Cpu0Subtarget.h

@@ -71,7 +71,7 @@ class Cpu0Subtarget : public Cpu0GenSubtargetInfo {
   }
 
   bool hasChapter5_1() const {
-    return false;
+    return true;
   }
 
   bool hasChapter6_1() const {

lib/Target/Cpu0/Cpu0TargetStreamer.h

@@ -0,0 +1,37 @@
+//===-- Cpu0TargetStreamer.h - Cpu0 Target Streamer ------------*- C++ -*--===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_CPU0_CPU0TARGETSTREAMER_H
+#define LLVM_LIB_TARGET_CPU0_CPU0TARGETSTREAMER_H
+
+#include "Cpu0Config.h"
+
+#include "llvm/MC/MCELFStreamer.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCStreamer.h"
+
+namespace llvm {
+
+class Cpu0TargetStreamer : public MCTargetStreamer {
+public:
+  Cpu0TargetStreamer(MCStreamer &S);
+};
+
+// This part is for ascii assembly output
+class Cpu0TargetAsmStreamer : public Cpu0TargetStreamer {
+  formatted_raw_ostream &OS;
+
+public:
+  Cpu0TargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
+};
+
+}
+
+#endif
+

lib/Target/Cpu0/InstPrinter/Cpu0InstPrinter.cpp

@@ -13,6 +13,7 @@
 
 #include "Cpu0InstPrinter.h"
 
+#include "MCTargetDesc/Cpu0MCExpr.h"
 #include "Cpu0InstrInfo.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/MC/MCExpr.h"

lib/Target/Cpu0/MCTargetDesc/CMakeLists.txt

@@ -2,6 +2,11 @@
 add_llvm_library(LLVMCpu0Desc
   Cpu0ABIInfo.cpp
   Cpu0MCAsmInfo.cpp
+  Cpu0AsmBackend.cpp
+  Cpu0MCCodeEmitter.cpp
+  Cpu0MCExpr.cpp
+  Cpu0ELFObjectWriter.cpp
+  Cpu0TargetStreamer.cpp
   Cpu0MCTargetDesc.cpp
   )
 

lib/Target/Cpu0/MCTargetDesc/Cpu0AsmBackend.cpp

@@ -0,0 +1,154 @@
+//===-- Cpu0AsmBackend.cpp - Cpu0 Asm Backend  ----------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the Cpu0AsmBackend class.
+//
+//===----------------------------------------------------------------------===//
+//
+
+#include "MCTargetDesc/Cpu0FixupKinds.h"
+#include "MCTargetDesc/Cpu0AsmBackend.h"
+
+#include "MCTargetDesc/Cpu0MCTargetDesc.h"
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCDirectives.h"
+#include "llvm/MC/MCELFObjectWriter.h"
+#include "llvm/MC/MCFixupKindInfo.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+//@adjustFixupValue {
+// Prepare value for the target space for it
+static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
+                                 MCContext *Ctx = nullptr) {
+
+  unsigned Kind = Fixup.getKind();
+
+  // Add/subtract and shift
+  switch (Kind) {
+  default:
+    return 0;
+  case FK_GPRel_4:
+  case FK_Data_4:
+  case Cpu0::fixup_Cpu0_LO16:
+    break;
+  case Cpu0::fixup_Cpu0_HI16:
+  case Cpu0::fixup_Cpu0_GOT:
+    // Get the higher 16-bits. Also add 1 if bit 15 is 1.
+    Value = ((Value + 0x8000) >> 16) & 0xffff;
+    break;
+  }
+
+  return Value;
+}
+//@adjustFixupValue }
+
+MCObjectWriter *
+Cpu0AsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
+  return createCpu0ELFObjectWriter(OS,
+    MCELFObjectTargetWriter::getOSABI(OSType), IsLittle);
+}
+
+/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
+/// data fragment, at the offset specified by the fixup and following the
+/// fixup kind as appropriate.
+void Cpu0AsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
+                                unsigned DataSize, uint64_t Value,
+                                bool IsPCRel) const {
+  MCFixupKind Kind = Fixup.getKind();
+  Value = adjustFixupValue(Fixup, Value);
+
+  if (!Value)
+    return; // Doesn't change encoding.
+
+  // Where do we start in the object
+  unsigned Offset = Fixup.getOffset();
+  // Number of bytes we need to fixup
+  unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
+  // Used to point to big endian bytes
+  unsigned FullSize;
+
+  switch ((unsigned)Kind) {
+  default:
+    FullSize = 4;
+    break;
+  }
+
+  // Grab current value, if any, from bits.
+  uint64_t CurVal = 0;
+
+  for (unsigned i = 0; i != NumBytes; ++i) {
+    unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
+    CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
+  }
+
+  uint64_t Mask = ((uint64_t)(-1) >>
+                    (64 - getFixupKindInfo(Kind).TargetSize));
+  CurVal |= Value & Mask;
+
+  // Write out the fixed up bytes back to the code/data bits.
+  for (unsigned i = 0; i != NumBytes; ++i) {
+    unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
+    Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
+  }
+}
+
+//@getFixupKindInfo {
+const MCFixupKindInfo &Cpu0AsmBackend::
+getFixupKindInfo(MCFixupKind Kind) const {
+  const static MCFixupKindInfo Infos[Cpu0::NumTargetFixupKinds] = {
+    // This table *must* be in same the order of fixup_* kinds in
+    // Cpu0FixupKinds.h.
+    //
+    // name                        offset  bits  flags
+    { "fixup_Cpu0_32",             0,     32,   0 },
+    { "fixup_Cpu0_HI16",           0,     16,   0 },
+    { "fixup_Cpu0_LO16",           0,     16,   0 },
+    { "fixup_Cpu0_GPREL16",        0,     16,   0 },
+    { "fixup_Cpu0_GOT",            0,     16,   0 },
+    { "fixup_Cpu0_GOT_HI16",       0,     16,   0 },
+    { "fixup_Cpu0_GOT_LO16",       0,     16,   0 }
+  };
+
+  if (Kind < FirstTargetFixupKind)
+    return MCAsmBackend::getFixupKindInfo(Kind);
+
+  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
+         "Invalid kind!");
+  return Infos[Kind - FirstTargetFixupKind];
+}
+//@getFixupKindInfo }
+
+/// WriteNopData - Write an (optimal) nop sequence of Count bytes
+/// to the given output. If the target cannot generate such a sequence,
+/// it should return an error.
+///
+/// \return - True on success.
+bool Cpu0AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+  return true;
+}
+
+// MCAsmBackend
+MCAsmBackend *llvm::createCpu0AsmBackendEL32(const Target &T,
+                                             const MCRegisterInfo &MRI,
+                                             const Triple &TT, StringRef CPU) {
+  return new Cpu0AsmBackend(T, TT.getOS(), /*IsLittle*/true);
+}
+
+MCAsmBackend *llvm::createCpu0AsmBackendEB32(const Target &T,
+                                             const MCRegisterInfo &MRI,
+                                             const Triple &TT, StringRef CPU) {
+  return new Cpu0AsmBackend(T, TT.getOS(), /*IsLittle*/false);
+}
+

lib/Target/Cpu0/MCTargetDesc/Cpu0AsmBackend.h

@@ -0,0 +1,88 @@
+//===-- Cpu0AsmBackend.h - Cpu0 Asm Backend  ------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the Cpu0AsmBackend class.
+//
+//===----------------------------------------------------------------------===//
+//
+
+#ifndef LLVM_LIB_TARGET_CPU0_MCTARGETDESC_CPU0ASMBACKEND_H
+#define LLVM_LIB_TARGET_CPU0_MCTARGETDESC_CPU0ASMBACKEND_H
+
+#include "Cpu0Config.h"
+
+#include "MCTargetDesc/Cpu0FixupKinds.h"
+#include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCAsmBackend.h"
+
+namespace llvm {
+
+class MCAssembler;
+struct MCFixupKindInfo;
+class Target;
+class MCObjectWriter;
+
+class Cpu0AsmBackend : public MCAsmBackend {
+  Triple::OSType OSType;
+  bool IsLittle; // Big or little endian
+
+public:
+  Cpu0AsmBackend(const Target &T, Triple::OSType _OSType, bool IsLittle)
+      : MCAsmBackend(), OSType(_OSType), IsLittle(IsLittle) {}
+
+  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
+
+  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
+                  uint64_t Value, bool IsPCRel) const override;
+
+  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
+
+  unsigned getNumFixupKinds() const override {
+    return Cpu0::NumTargetFixupKinds;
+  }
+
+  /// @name Target Relaxation Interfaces
+  /// @{
+
+  /// MayNeedRelaxation - Check whether the given instruction may need
+  /// relaxation.
+  ///
+  /// \param Inst - The instruction to test.
+  bool mayNeedRelaxation(const MCInst &Inst) const override {
+    return false;
+  }
+
+  /// fixupNeedsRelaxation - Target specific predicate for whether a given
+  /// fixup requires the associated instruction to be relaxed.
+   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
+                             const MCRelaxableFragment *DF,
+                             const MCAsmLayout &Layout) const override {
+    // FIXME.
+    llvm_unreachable("RelaxInstruction() unimplemented");
+    return false;
+  }
+
+  /// RelaxInstruction - Relax the instruction in the given fragment
+  /// to the next wider instruction.
+  ///
+  /// \param Inst - The instruction to relax, which may be the same
+  /// as the output.
+  /// \param [out] Res On return, the relaxed instruction.
+  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCInst &Res) const override {}
+
+  /// @}
+
+  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+}; // class Cpu0AsmBackend
+
+} // namespace
+
+#endif
+

lib/Target/Cpu0/MCTargetDesc/Cpu0BaseInfo.h

@@ -16,6 +16,7 @@
 
 #include "Cpu0Config.h"
 
+#include "Cpu0FixupKinds.h"
 #include "Cpu0MCTargetDesc.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/Support/DataTypes.h"