GitHub - muhammedkamal/DMA-: DMA Project using Verilog HDL

Name		Name	Last commit message	Last commit date
Latest commit History 14 Commits
DMA_Project.v		DMA_Project.v
Processor.v		Processor.v
RegFile.v		RegFile.v
TestBench.v		TestBench.v
buffermemory.mem		buffermemory.mem
buffermemory1.mem		buffermemory1.mem
buffermemory2.mem		buffermemory2.mem
instructionfile.txt		instructionfile.txt
interrupt.mem		interrupt.mem
interrupt1.mem		interrupt1.mem
interrupt2.mem		interrupt2.mem
iodevice.v		iodevice.v
iodevice1.v		iodevice1.v
iodevice2.v		iodevice2.v
memory.mem		memory.mem
memory.v		memory.v
pro.v		pro.v
tagme3test.v		tagme3test.v