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[tricore] TRICORE processor module
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mumbel committed Jul 17, 2019
1 parent ac47453 commit 7fc76db
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8 changes: 8 additions & 0 deletions Ghidra/Processors/tricore/build.gradle
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apply plugin: 'eclipse'
eclipse.project.name = 'Processors tricore'

/*********************************************************************************
* Imports
*********************************************************************************/
apply from: "$rootProject.projectDir/gradleScripts/processorUtils.gradle"

19 changes: 19 additions & 0 deletions Ghidra/Processors/tricore/certification.manifest
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##VERSION: 2.0
.classpath||GHIDRA||||END|
.project||GHIDRA||||END|
Module.manifest||GHIDRA||||END|
build.gradle||GHIDRA||||END|
data/build.xml||GHIDRA||||END|
data/languages/tricore.cspec||GHIDRA||||END|
data/languages/tricore.ldefs||GHIDRA||||END|
data/languages/tricore.pspec||GHIDRA||||END|
data/languages/tc29x.pspec||GHIDRA||||END|
data/languages/tc172x.pspec||GHIDRA||||END|
data/languages/tc176x.pspec||GHIDRA||||END|
data/languages/tricore.slaspec||GHIDRA||||END|
data/languages/tricore.sinc||GHIDRA||||END|
data/languages/tricore.pcp.sinc||GHIDRA||||END|
data/languages/tricore.dwarf||GHIDRA||||END|
data/manuals/tricore.idx||GHIDRA||||END|
data/manuals/tricore2.idx||GHIDRA||||END|

2,342 changes: 2,342 additions & 0 deletions Ghidra/Processors/tricore/data/languages/tc172x.pspec

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1,523 changes: 1,523 additions & 0 deletions Ghidra/Processors/tricore/data/languages/tc176x.pspec

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3,726 changes: 3,726 additions & 0 deletions Ghidra/Processors/tricore/data/languages/tc29x.pspec

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116 changes: 116 additions & 0 deletions Ghidra/Processors/tricore/data/languages/tricore.cspec
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<?xml version="1.0" encoding="UTF-8"?>

<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="8" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<global>
<register name="a8"/>
<register name="a9"/>
<register name="p8"/>
<register name="a0"/>
<register name="a1"/>
<register name="p0"/>
<range space="ram"/>
</global>
<returnaddress>
<register name="a11"/>
</returnaddress>
<stackpointer register="a10" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="4">
<!-- This is the first non pointer -->
<register name="a4"/>
</pentry>
<pentry minsize="1" maxsize="4">
<!-- This is the first non pointer -->
<register name="d4"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a5"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="d5"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a6"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="d6"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a7"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="d7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="16" space="ram"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="a2"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="d2"/>
</pentry>
</output>
<unaffected>
<register name="d8"/>
<register name="d9"/>
<register name="d10"/>
<register name="d11"/>
<register name="d12"/>
<register name="d13"/>
<register name="d14"/>
<register name="d15"/>
<register name="a10"/>
<register name="a11"/>
<register name="a12"/>
<register name="a13"/>
<register name="a14"/>
<register name="a15"/>
</unaffected>
</prototype>
</default_proto>
<callotherfixup targetop="saveCallerState">
<pcode>
<input name="fcx"/>
<input name="lcx"/>
<input name="pcxi"/>
<body><![CDATA[
tmpptr:4 = 0;
]]></body>
</pcode>
</callotherfixup>

<callotherfixup targetop="restoreCallerState">
<pcode>
<input name="fcx"/>
<input name="lcx"/>
<input name="pcxi"/>
<body><![CDATA[
tmpptr:4 = 0;
]]></body>
</pcode>
</callotherfixup>
</compiler_spec>
27 changes: 27 additions & 0 deletions Ghidra/Processors/tricore/data/languages/tricore.dwarf
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<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="d0" auto_count="16"/> <!-- d0..d15 -->
<register_mapping dwarf="16" ghidra="a0" auto_count="10"/> <!-- d0.d9 -->
<register_mapping dwarf="26" ghidra="a10" stackpointer="true"/>
<register_mapping dwarf="27" ghidra="a11" auto_count="5"/> <!-- d11..d15 -->
<register_mapping dwarf="32" ghidra="e0"/>
<register_mapping dwarf="33" ghidra="e2"/>
<register_mapping dwarf="34" ghidra="e4"/>
<register_mapping dwarf="35" ghidra="e6"/>
<register_mapping dwarf="36" ghidra="e8"/>
<register_mapping dwarf="37" ghidra="e10"/>
<register_mapping dwarf="38" ghidra="e12"/>
<register_mapping dwarf="39" ghidra="e14"/>
<register_mapping dwarf="40" ghidra="PSW"/>
<register_mapping dwarf="41" ghidra="PCXI"/>
<register_mapping dwarf="42" ghidra="PC"/>
<register_mapping dwarf="43" ghidra="FCX"/>
<register_mapping dwarf="44" ghidra="LCX"/>
<register_mapping dwarf="45" ghidra="ISP"/>
<register_mapping dwarf="46" ghidra="ICR"/>
<register_mapping dwarf="47" ghidra="PIPN"/>
<register_mapping dwarf="48" ghidra="BIV"/>
<register_mapping dwarf="49" ghidra="BTV"/>
</register_mappings>
<call_frame_cfa value="4"/>
</dwarf>
57 changes: 57 additions & 0 deletions Ghidra/Processors/tricore/data/languages/tricore.ldefs
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<?xml version="1.0" encoding="UTF-8"?>

<language_definitions>

<language processor="tricore"
endian="little"
size="32"
variant="default"
version="1.6"
slafile="tricore.sla"
processorspec="tricore.pspec"
manualindexfile="../manuals/tricore2.idx"
id="tricore:LE:32:default">
<description>Siemens Tricore Embedded Processor</description>
<compiler name="default" spec="tricore.cspec" id="default"/>
<external_name tool="DWARF.register.mapping.file" name="tricore.dwarf"/>
</language>
<language processor="tricore"
endian="little"
size="32"
variant="TC29x"
version="1.6"
slafile="tricore.sla"
processorspec="tc29x.pspec"
manualindexfile="../manuals/tricore2.idx"
id="tricore:LE:32:tc29x">
<description>Siemens Tricore Embedded Processor TC29x</description>
<compiler name="default" spec="tricore.cspec" id="default"/>
<external_name tool="DWARF.register.mapping.file" name="tricore.dwarf"/>
</language>
<language processor="tricore"
endian="little"
size="32"
variant="TC172x"
version="1.3"
slafile="tricore.sla"
processorspec="tc172x.pspec"
manualindexfile="../manuals/tricore.idx"
id="tricore:LE:32:tc172x">
<description>Siemens Tricore Embedded Processor TC1724/TC1728</description>
<compiler name="default" spec="tricore.cspec" id="default"/>
<external_name tool="DWARF.register.mapping.file" name="tricore.dwarf"/>
</language>
<language processor="tricore"
endian="little"
size="32"
variant="TC176x"
version="1.3"
slafile="tricore.sla"
processorspec="tc176x.pspec"
manualindexfile="../manuals/tricore.idx"
id="tricore:LE:32:tc176x">
<description>Siemens Tricore Embedded Processor TC1762/TC1766</description>
<compiler name="default" spec="tricore.cspec" id="default"/>
<external_name tool="DWARF.register.mapping.file" name="tricore.dwarf"/>
</language>
</language_definitions>

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