“mmRISC_1” is a RISC-V compliant CPU core with RV32IM[A][F]C ISA for MCU.
The “mmRISC” stands for “much more RISC”.
For details, please refer PDF file under doc directory.
(1) Added cJTAG (2-wire compact JTAG) as the debug interface. You can select the debug interface from JTAG or cJTAG.
(2) Added alternative Halt-On-Reset, controlled by a hardware input signal level, instead of the one in standard RISC-V debug function.
(3) Added a new JTAG DR register for user’s multi purposes, for example, to configure the operation modes of the SoC from JTAG/cJTAG interface.
(4) The number of 32bit secure code for authentication is expanded from one to two.
(5) Supported low power mode (STBY).
(6) Added precise verification methods for floating point operations. Corrected RTL code in conversion from float to int (cpu_fpu32.v).
(7) Added a application program; Tic-Tac-Toe AI Game on Touch LCD panel.
Some files and directories were lacked in riscv-arch-test and riscv-tests. Repaired them.
(1) In simulation/modelsim/mmRISC_Simulation, simulation/modelsim/riscv-tests and simulation/modelsim/riscv-arch-test, corrected test banch top RTL (tb_TOP.v) and simulation script (sim_TOP.do) in each directory.
(2) Correct minor typo in comment of uart.v.
(3) Body RTL codes of mmRISC and its SOC(FPGA) do not have any bugs.
(1) Added SPI, one more I2C.
(2) Wrote know-hows in Technical Reference Manual to use Raspberry Pi as a Development Environment including OpenOCD interface. Added an example of openocd script for Raspberry Pi in directory "openocd".
(3) In application mmRISC_SampleCPU, added access of Acceleration Sensor on MAX10-Lite board through I2C interface.
(4) Added new application mmRISC_TouchLCD which handles Adafruit-2-8-tft-touch-shield-v2 with Resistive Touch Panel or Capacitive Touch Panel for Arduino.
(5) In each sample program, baud rate of UART is unified to 115200bps.
2022.05.01 Fixed Operation of RV32F Instruction in which source registers are FRn and destination register is XRn.
BUG : When RV32F Instruction in which destination register is XRn, such as FMV.X.W, FCLASS.S, FCMP,FCVT.W(U).S and FCMP.S, is followed by an instruction in which above XRn is used as source register, sometimes the source value is old one that has not been updated by the RV32F instruction.
WHY : Incorrect instruction stallings.
FIX : Make the RV32F instruction in which its destination is XRn be multicycle instruction in each. Updated cpu_pipeline.v and cpu_fpu32.v.
Followings are updated.
(1) common/defines.v is divided into defines_core.v for mmRISC Core and defines_chip.v for Chip System. (defines.v is not used any more.)
(2) Simple I2C Core is added in FPGA. Related modifications are applied in RTL and Verification resources. Simple CPU Sample Program supports I2C which comunicates with Accelerometer Sensor on MAX10-Lite board.
(3) Simple SDRAM Interface logic is added in FPGA which accesses 64MB SDRAM on MAX10-Lite board.
0x80000000-( 64GB) SDRAM
0x88000000-( 48KB) Internal Data RAM
0x90000000-(128KB) Internal Instruction RAM
- The Technical Reference Manual has not been updated along with above updates. Please wait for a while.
BUG1: FMV W.X and FMV X.W sometimes could not transfer correct data according to pipeline stall or wait-cycle timing.
WHY1: EX_FPU_DSTDATA was active only when EX_ALU_DST1 was asserted.
FIX1: EX_FPU_DSTDATA is connected from ex_busZ directly in cpu_datapath.v. EX_FPU_SRCDATA is stretched until next updating in cpu_fpu32.v.
BUG2: In FLW (load) followed by FMADD.S/FMSUB.S/FNMSUB.S/FNMADD.S, FMADDs did not use latest loaded data in src3.
WHY2: The register contention check between FLW's destination and FMADD's source 3 (src3) was not implemented.
FIX2: Contention check between FLW's destination and FMADD's source 3 (src3) is implemented in cpu_pipeline.v.
BUG: Sometimes ignored HALT/RESUME Requests from Debugger during ID Stage is being stalled due to memory wait cycles.
WHY: DBG_HALT_ACK and DBG_RESUME_ACK are asserted in one cycle even during ID stallings. If these ACK signals are asserted, corresponding DBG_HALT_REQ and DBG_RESUME_REQ are immediately negated, then the pipeline control may ignore DBG_HALT_REQ and DBG_RESUME_REQ.
FIX: DBG_HALT_ACK and DBG_RESUME_ACK are asserted only at last of ID stages after its stalls in cpu_pipeline.v.
Followings are updated. Main RTL Body of mmRISC is not modified due to no bugs found yet.
(1) Added MRET and WFI descriptions in Technical Reference Manual Rev.02.
(2) Supported Questa as logic simulator. To do so, add an option -voptargs="+acc" in vsim command.
(3) Supported Initialization of Instruction RAM in FPGA using .mif file. A conversion tool hex2mif is added in tools directory.
(4) Updated JTAG interface schematic.
(5) Changed operation of application mmRISC_SampleCPU.
(6) Add a retro text video game StarTrek as an application.
If you use Questa Sim to simulate mmRISC-1, please add an option -voptargs="+acc" in vsim command.
RV32IM[A][F]C (configurable)
Multi Harts Supported, 1 to 2^20 (configurable)
For Integer : 3 to 5 stages
For Floating Point : 3 to 6 stages
Integer Multiplication MUL/MULH/MULHSU/MULHU : 1 cycle
Integer Division DIV/DIVU/REM/REMU : 33 cyles (Non-Restoring Method)
Floating Operations
FADD.S/FSUB.S/FMUL.S/FMADD.S/FMSUB.S/FNMADD.S/FNMSUB.S : 1 cycle
FDIV.S : 11 cycles (Goldschmidt's Algorithm)
FSQRT.S : 19 cycles (Goldschmidt's Algorithm)
The convergence loop counts for FDIV.S and FSQRT.S can be configured by software.
External Debug Support Ver.0.13.2 with JTAG Interface
Run / Stop / Step <br)
Abstract Command to access Register and Memory
System Bus Access for Memory
Hardware Break Points (Instruction / Data) x 4 (Configurable)
Instruction Count Break Point x 1
Machine-Mode (M-Mode) only
IRQ_EXT : External Interrupt
IRQ_MSOFT : Machine Software Interrupt
IRQ_MTIME : Machine Timer Interrupt
IRQ[63:0] : User IRQ, 64 inputs / Vectored Supported / 16 priority levels for each
64bits MCYCLE (Clock Cycle Counter)
64bits MINSTRET (Instruction Retired Counter)
64bits MTIME (Memory Mapped Interrupt Timer)
Instruction Fetch Bus
Data Bus multiplexed with Debugger Abstract Command
LR/SC Monitor Bus
Debugger System Bus
Verilog-2001 / System Verilog
Vector Simluation
RISC-V Compliance Test “riscv-arch-test” for I/C/M/Zifence/Privileged
RISC-V Unit Test “riscv-tests” including Atomic and Floating Point ISA
Comparison between TestFloat and RV32F on FPGA
DE10-Lite Board (Intel MAX 10 10M50DAF484C7G)
cTAG/JTAG Interface (FT2232D)
Eclipse + Gnu Toolchains + OpenOCD
Simple CPU Sample Program
Simple FPU Sample Program
FreeRTOS Porting (Blinky)
Dhrystone Benchmark
Coremark Benchmark
Retro StarTrek Game
Touch LCD Panel Demo : Paint and Gravity Ball
Touch LCD Panel Demo : Human vs CPU Tic-Tac-Toe