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rtl838x.c
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rtl838x.c
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// SPDX-License-Identifier: GPL-2.0-only
#include <asm/mach-rtl838x/mach-rtl83xx.h>
#include <net/nexthop.h>
#include "rtl83xx.h"
extern struct mutex smi_lock;
// see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c
/* Definition of the RTL838X-specific template field IDs as used in the PIE */
enum template_field_id {
TEMPLATE_FIELD_SPMMASK = 0,
TEMPLATE_FIELD_SPM0 = 1, // Source portmask ports 0-15
TEMPLATE_FIELD_SPM1 = 2, // Source portmask ports 16-28
TEMPLATE_FIELD_RANGE_CHK = 3,
TEMPLATE_FIELD_DMAC0 = 4, // Destination MAC [15:0]
TEMPLATE_FIELD_DMAC1 = 5, // Destination MAC [31:16]
TEMPLATE_FIELD_DMAC2 = 6, // Destination MAC [47:32]
TEMPLATE_FIELD_SMAC0 = 7, // Source MAC [15:0]
TEMPLATE_FIELD_SMAC1 = 8, // Source MAC [31:16]
TEMPLATE_FIELD_SMAC2 = 9, // Source MAC [47:32]
TEMPLATE_FIELD_ETHERTYPE = 10, // Ethernet typ
TEMPLATE_FIELD_OTAG = 11, // Outer VLAN tag
TEMPLATE_FIELD_ITAG = 12, // Inner VLAN tag
TEMPLATE_FIELD_SIP0 = 13, // IPv4 or IPv6 source IP[15:0] or ARP/RARP
// source protocol address in header
TEMPLATE_FIELD_SIP1 = 14, // IPv4 or IPv6 source IP[31:16] or ARP/RARP
TEMPLATE_FIELD_DIP0 = 15, // IPv4 or IPv6 destination IP[15:0]
TEMPLATE_FIELD_DIP1 = 16, // IPv4 or IPv6 destination IP[31:16]
TEMPLATE_FIELD_IP_TOS_PROTO = 17, // IPv4 TOS/IPv6 traffic class and
// IPv4 proto/IPv6 next header fields
TEMPLATE_FIELD_L34_HEADER = 18, // packet with extra tag and IPv6 with auth, dest,
// frag, route, hop-by-hop option header,
// IGMP type, TCP flag
TEMPLATE_FIELD_L4_SPORT = 19, // TCP/UDP source port
TEMPLATE_FIELD_L4_DPORT = 20, // TCP/UDP destination port
TEMPLATE_FIELD_ICMP_IGMP = 21,
TEMPLATE_FIELD_IP_RANGE = 22,
TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, // Field selector mask
TEMPLATE_FIELD_FIELD_SELECTOR_0 = 24,
TEMPLATE_FIELD_FIELD_SELECTOR_1 = 25,
TEMPLATE_FIELD_FIELD_SELECTOR_2 = 26,
TEMPLATE_FIELD_FIELD_SELECTOR_3 = 27,
TEMPLATE_FIELD_SIP2 = 28, // IPv6 source IP[47:32]
TEMPLATE_FIELD_SIP3 = 29, // IPv6 source IP[63:48]
TEMPLATE_FIELD_SIP4 = 30, // IPv6 source IP[79:64]
TEMPLATE_FIELD_SIP5 = 31, // IPv6 source IP[95:80]
TEMPLATE_FIELD_SIP6 = 32, // IPv6 source IP[111:96]
TEMPLATE_FIELD_SIP7 = 33, // IPv6 source IP[127:112]
TEMPLATE_FIELD_DIP2 = 34, // IPv6 destination IP[47:32]
TEMPLATE_FIELD_DIP3 = 35, // IPv6 destination IP[63:48]
TEMPLATE_FIELD_DIP4 = 36, // IPv6 destination IP[79:64]
TEMPLATE_FIELD_DIP5 = 37, // IPv6 destination IP[95:80]
TEMPLATE_FIELD_DIP6 = 38, // IPv6 destination IP[111:96]
TEMPLATE_FIELD_DIP7 = 39, // IPv6 destination IP[127:112]
TEMPLATE_FIELD_FWD_VID = 40, // Forwarding VLAN-ID
TEMPLATE_FIELD_FLOW_LABEL = 41,
};
/*
* The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to
* be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet
* Inspection Engine's buffer. The following defines the field contents for each of the fixed
* templates. Additionally, 3 user-definable templates can be set up via the definitions
* in RTL838X_ACL_TMPLTE_CTRL control registers.
* TODO: See all src/app/diag_v2/src/diag_pie.c
*/
#define N_FIXED_TEMPLATES 5
static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
{
{
TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_OTAG,
TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_RANGE_CHK
}, {
TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_ITAG,
TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
}, {
TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,
TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1
}, {
TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,
TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO
}, {
TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_ITAG,
TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
},
};
void rtl838x_print_matrix(void)
{
unsigned volatile int *ptr8;
int i;
ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
for (i = 0; i < 28; i += 8)
pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
pr_debug("CPU_PORT> %8x\n", ptr8[28]);
}
static inline int rtl838x_port_iso_ctrl(int p)
{
return RTL838X_PORT_ISO_CTRL(p);
}
static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
{
sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));
}
static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
{
sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));
}
static inline int rtl838x_tbl_access_data_0(int i)
{
return RTL838X_TBL_ACCESS_DATA_0(i);
}
static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
{
u32 v;
// Read VLAN table (0) via register 0
struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
rtl_table_read(r, vlan);
info->tagged_ports = sw_r32(rtl_table_data(r, 0));
v = sw_r32(rtl_table_data(r, 1));
pr_debug("VLAN_READ %d: %016llx %08x\n", vlan, info->tagged_ports, v);
rtl_table_release(r);
info->profile_id = v & 0x7;
info->hash_mc_fid = !!(v & 0x8);
info->hash_uc_fid = !!(v & 0x10);
info->fid = (v >> 5) & 0x3f;
// Read UNTAG table (0) via table register 1
r = rtl_table_get(RTL8380_TBL_1, 0);
rtl_table_read(r, vlan);
info->untagged_ports = sw_r32(rtl_table_data(r, 0));
rtl_table_release(r);
}
static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
{
u32 v;
// Access VLAN table (0) via register 0
struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
sw_w32(info->tagged_ports, rtl_table_data(r, 0));
v = info->profile_id;
v |= info->hash_mc_fid ? 0x8 : 0;
v |= info->hash_uc_fid ? 0x10 : 0;
v |= ((u32)info->fid) << 5;
sw_w32(v, rtl_table_data(r, 1));
rtl_table_write(r, vlan);
rtl_table_release(r);
}
static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
{
// Access UNTAG table (0) via register 1
struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0);
sw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0));
rtl_table_write(r, vlan);
rtl_table_release(r);
}
/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
*/
static void rtl838x_vlan_fwd_on_inner(int port, bool is_set)
{
if (is_set)
sw_w32_mask(BIT(port), 0, RTL838X_VLAN_PORT_FWD);
else
sw_w32_mask(0, BIT(port), RTL838X_VLAN_PORT_FWD);
}
static u64 rtl838x_l2_hash_seed(u64 mac, u32 vid)
{
return mac << 12 | vid;
}
/*
* Applies the same hash algorithm as the one used currently by the ASIC to the seed
* and returns a key into the L2 hash table
*/
static u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
{
u32 h1, h2, h3, h;
if (sw_r32(priv->r->l2_ctrl_0) & 1) {
h1 = (seed >> 11) & 0x7ff;
h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
h2 = (seed >> 33) & 0x7ff;
h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
h3 = (seed >> 44) & 0x7ff;
h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
} else {
h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff)
^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
}
return h;
}
static inline int rtl838x_mac_force_mode_ctrl(int p)
{
return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
}
static inline int rtl838x_mac_port_ctrl(int p)
{
return RTL838X_MAC_PORT_CTRL(p);
}
static inline int rtl838x_l2_port_new_salrn(int p)
{
return RTL838X_L2_PORT_NEW_SALRN(p);
}
static inline int rtl838x_l2_port_new_sa_fwd(int p)
{
return RTL838X_L2_PORT_NEW_SA_FWD(p);
}
static inline int rtl838x_mac_link_spd_sts(int p)
{
return RTL838X_MAC_LINK_SPD_STS(p);
}
inline static int rtl838x_trk_mbr_ctr(int group)
{
return RTL838X_TRK_MBR_CTR + (group << 2);
}
/*
* Fills an L2 entry structure from the SoC registers
*/
static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
{
/* Table contains different entry types, we need to identify the right one:
* Check for MC entries, first
* In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to
* identify valid entries
*/
e->is_ip_mc = !!(r[0] & BIT(22));
e->is_ipv6_mc = !!(r[0] & BIT(21));
e->type = L2_INVALID;
if (!e->is_ip_mc && !e->is_ipv6_mc) {
e->mac[0] = (r[1] >> 20);
e->mac[1] = (r[1] >> 12);
e->mac[2] = (r[1] >> 4);
e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
e->mac[4] = (r[2] >> 20);
e->mac[5] = (r[2] >> 12);
e->rvid = r[2] & 0xfff;
e->vid = r[0] & 0xfff;
/* Is it a unicast entry? check multicast bit */
if (!(e->mac[0] & 1)) {
e->is_static = !!((r[0] >> 19) & 1);
e->port = (r[0] >> 12) & 0x1f;
e->block_da = !!(r[1] & BIT(30));
e->block_sa = !!(r[1] & BIT(31));
e->suspended = !!(r[1] & BIT(29));
e->next_hop = !!(r[1] & BIT(28));
if (e->next_hop) {
pr_debug("Found next hop entry, need to read extra data\n");
e->nh_vlan_target = !!(r[0] & BIT(9));
e->nh_route_id = r[0] & 0x1ff;
e->vid = e->rvid;
}
e->age = (r[0] >> 17) & 0x3;
e->valid = true;
/* A valid entry has one of mutli-cast, aging, sa/da-blocking,
* next-hop or static entry bit set */
if (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000))
e->valid = false;
else
e->type = L2_UNICAST;
} else { // L2 multicast
pr_debug("Got L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]);
e->valid = true;
e->type = L2_MULTICAST;
e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
}
} else { // IPv4 and IPv6 multicast
e->valid = true;
e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
e->mc_gip = (r[1] << 20) | (r[2] >> 12);
e->rvid = r[2] & 0xfff;
}
if (e->is_ip_mc)
e->type = IP4_MULTICAST;
if (e->is_ipv6_mc)
e->type = IP6_MULTICAST;
}
/*
* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
*/
static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
{
u64 mac = ether_addr_to_u64(e->mac);
if (!e->valid) {
r[0] = r[1] = r[2] = 0;
return;
}
r[0] = e->is_ip_mc ? BIT(22) : 0;
r[0] |= e->is_ipv6_mc ? BIT(21) : 0;
if (!e->is_ip_mc && !e->is_ipv6_mc) {
r[1] = mac >> 20;
r[2] = (mac & 0xfffff) << 12;
/* Is it a unicast entry? check multicast bit */
if (!(e->mac[0] & 1)) {
r[0] |= e->is_static ? BIT(19) : 0;
r[0] |= (e->port & 0x3f) << 12;
r[0] |= e->vid;
r[1] |= e->block_da ? BIT(30) : 0;
r[1] |= e->block_sa ? BIT(31) : 0;
r[1] |= e->suspended ? BIT(29) : 0;
r[2] |= e->rvid & 0xfff;
if (e->next_hop) {
r[1] |= BIT(28);
r[0] |= e->nh_vlan_target ? BIT(9) : 0;
r[0] |= e->nh_route_id & 0x1ff;
}
r[0] |= (e->age & 0x3) << 17;
} else { // L2 Multicast
r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
r[2] |= e->rvid & 0xfff;
r[0] |= e->vid & 0xfff;
pr_debug("FILL MC: %08x %08x %08x\n", r[0], r[1], r[2]);
}
} else { // IPv4 and IPv6 multicast
r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
r[1] = e->mc_gip >> 20;
r[2] = e->mc_gip << 12;
r[2] |= e->rvid;
}
}
/*
* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
* hash is the id of the bucket and pos is the position of the entry in that bucket
* The data read from the SoC is filled into rtl838x_l2_entry
*/
static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
{
u64 entry;
u32 r[3];
struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); // Access L2 Table 0
u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
int i;
rtl_table_read(q, idx);
for (i= 0; i < 3; i++)
r[i] = sw_r32(rtl_table_data(q, i));
rtl_table_release(q);
rtl838x_fill_l2_entry(r, e);
if (!e->valid)
return 0;
entry = (((u64) r[1]) << 32) | (r[2]); // mac and vid concatenated as hash seed
return entry;
}
static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
{
u32 r[3];
struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0);
int i;
u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
rtl838x_fill_l2_row(r, e);
for (i= 0; i < 3; i++)
sw_w32(r[i], rtl_table_data(q, i));
rtl_table_write(q, idx);
rtl_table_release(q);
}
static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
{
u64 entry;
u32 r[3];
struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1
int i;
rtl_table_read(q, idx);
for (i= 0; i < 3; i++)
r[i] = sw_r32(rtl_table_data(q, i));
rtl_table_release(q);
rtl838x_fill_l2_entry(r, e);
if (!e->valid)
return 0;
pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
// Return MAC with concatenated VID ac concatenated ID
entry = (((u64) r[1]) << 32) | r[2];
return entry;
}
static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e)
{
u32 r[3];
struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1
int i;
rtl838x_fill_l2_row(r, e);
for (i= 0; i < 3; i++)
sw_w32(r[i], rtl_table_data(q, i));
rtl_table_write(q, idx);
rtl_table_release(q);
}
static u64 rtl838x_read_mcast_pmask(int idx)
{
u32 portmask;
// Read MC_PMSK (2) via register RTL8380_TBL_L2
struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
rtl_table_read(q, idx);
portmask = sw_r32(rtl_table_data(q, 0));
rtl_table_release(q);
return portmask;
}
static void rtl838x_write_mcast_pmask(int idx, u64 portmask)
{
// Access MC_PMSK (2) via register RTL8380_TBL_L2
struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
sw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0));
rtl_table_write(q, idx);
rtl_table_release(q);
}
static void rtl838x_vlan_profile_setup(int profile)
{
u32 pmask_id = UNKNOWN_MC_PMASK;
// Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding
u32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19;
sw_w32(p, RTL838X_VLAN_PROFILE(profile));
/* RTL8380 and RTL8390 use an index into the portmask table to set the
* unknown multicast portmask, setup a default at a safe location
* On RTL93XX, the portmask is directly set in the profile,
* see e.g. rtl9300_vlan_profile_setup
*/
rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x1fffffff);
}
static void rtl838x_l2_learning_setup(void)
{
/* Set portmask for broadcast traffic and unknown unicast address flooding
* to the reserved entry in the portmask table used also for
* multicast flooding */
sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL838X_L2_FLD_PMSK);
/* Enable learning constraint system-wide (bit 0), per-port (bit 1)
* and per vlan (bit 2) */
sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN);
// Limit learning to maximum: 16k entries, after that just flood (bits 0-1)
sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT);
// Do not trap ARP packets to CPU_PORT
sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL);
}
static void rtl838x_enable_learning(int port, bool enable)
{
// Limit learning to maximum: 32k entries, after that just flood (bits 0-1)
if (enable) {
// flood after 32k entries
sw_w32((0x3fff << 2) | 0, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
} else {
// just forward
sw_w32(0, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
}
}
static void rtl838x_enable_flood(int port, bool enable)
{
u32 flood_mask = sw_r32(RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
if (enable) {
// flood
flood_mask &= ~3;
flood_mask |= 0;
sw_w32(flood_mask, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
} else {
// drop (bit 1)
flood_mask &= ~3;
flood_mask |= 1;
sw_w32(flood_mask, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
}
}
static void rtl838x_enable_mcast_flood(int port, bool enable)
{
}
static void rtl838x_enable_bcast_flood(int port, bool enable)
{
}
static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
{
int i;
u32 cmd = 1 << 15 /* Execute cmd */
| 1 << 14 /* Read */
| 2 << 12 /* Table type 0b10 */
| (msti & 0xfff);
priv->r->exec_tbl0_cmd(cmd);
for (i = 0; i < 2; i++)
port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
}
static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
{
int i;
u32 cmd = 1 << 15 /* Execute cmd */
| 0 << 14 /* Write */
| 2 << 12 /* Table type 0b10 */
| (msti & 0xfff);
for (i = 0; i < 2; i++)
sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
priv->r->exec_tbl0_cmd(cmd);
}
u64 rtl838x_traffic_get(int source)
{
return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source));
}
void rtl838x_traffic_set(int source, u64 dest_matrix)
{
rtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source));
}
void rtl838x_traffic_enable(int source, int dest)
{
rtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source));
}
void rtl838x_traffic_disable(int source, int dest)
{
rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source));
}
/*
* Enables or disables the EEE/EEEP capability of a port
*/
static void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
{
u32 v;
// This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP
if (port >= 24)
return;
pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
v = enable ? 0x3 : 0x0;
// Set EEE state for 100 (bit 9) & 1000MBit (bit 10)
sw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port));
// Set TX/RX EEE state
if (enable) {
sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
} else {
sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
}
priv->ports[port].eee_enabled = enable;
}
/*
* Get EEE own capabilities and negotiation result
*/
static int rtl838x_eee_port_ability(struct rtl838x_switch_priv *priv,
struct ethtool_eee *e, int port)
{
u64 link;
if (port >= 24)
return 0;
link = rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS);
if (!(link & BIT(port)))
return 0;
if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(9))
e->advertised |= ADVERTISED_100baseT_Full;
if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(10))
e->advertised |= ADVERTISED_1000baseT_Full;
if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
e->lp_advertised = ADVERTISED_100baseT_Full;
e->lp_advertised |= ADVERTISED_1000baseT_Full;
return 1;
}
return 0;
}
static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
{
int i;
pr_info("Setting up EEE, state: %d\n", enable);
sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
/* Set timers for EEE */
sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
// Enable EEE MAC support on ports
for (i = 0; i < priv->cpu_port; i++) {
if (priv->ports[i].phy)
rtl838x_port_eee_set(priv, i, enable);
}
priv->eee_enabled = enable;
}
static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
{
int block = index / PIE_BLOCK_SIZE;
u32 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
// Make sure rule-lookup is enabled in the block
if (!(block_state & BIT(block)))
sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
}
static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
{
int block_from = index_from / PIE_BLOCK_SIZE;
int block_to = index_to / PIE_BLOCK_SIZE;
u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
int block;
u32 block_state;
pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
mutex_lock(&priv->reg_mutex);
// Remember currently active blocks
block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
// Make sure rule-lookup is disabled in the relevant blocks
for (block = block_from; block <= block_to; block++) {
if (block_state & BIT(block))
sw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL);
}
// Write from-to and execute bit into control register
sw_w32(v, RTL838X_ACL_CLR_CTRL);
// Wait until command has completed
do {
} while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0));
// Re-enable rule lookup
for (block = block_from; block <= block_to; block++) {
if (!(block_state & BIT(block)))
sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
}
mutex_unlock(&priv->reg_mutex);
}
/*
* Reads the intermediate representation of the templated match-fields of the
* PIE rule in the pie_rule structure and fills in the raw data fields in the
* raw register space r[].
* The register space configuration size is identical for the RTL8380/90 and RTL9300,
* however the RTL9310 has 2 more registers / fields and the physical field-ids
* are specific to every platform.
*/
static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
{
int i;
enum template_field_id field_type;
u16 data, data_m;
for (i = 0; i < N_FIXED_FIELDS; i++) {
field_type = t[i];
data = data_m = 0;
switch (field_type) {
case TEMPLATE_FIELD_SPM0:
data = pr->spm;
data_m = pr->spm_m;
break;
case TEMPLATE_FIELD_SPM1:
data = pr->spm >> 16;
data_m = pr->spm_m >> 16;
break;
case TEMPLATE_FIELD_OTAG:
data = pr->otag;
data_m = pr->otag_m;
break;
case TEMPLATE_FIELD_SMAC0:
data = pr->smac[4];
data = (data << 8) | pr->smac[5];
data_m = pr->smac_m[4];
data_m = (data_m << 8) | pr->smac_m[5];
break;
case TEMPLATE_FIELD_SMAC1:
data = pr->smac[2];
data = (data << 8) | pr->smac[3];
data_m = pr->smac_m[2];
data_m = (data_m << 8) | pr->smac_m[3];
break;
case TEMPLATE_FIELD_SMAC2:
data = pr->smac[0];
data = (data << 8) | pr->smac[1];
data_m = pr->smac_m[0];
data_m = (data_m << 8) | pr->smac_m[1];
break;
case TEMPLATE_FIELD_DMAC0:
data = pr->dmac[4];
data = (data << 8) | pr->dmac[5];
data_m = pr->dmac_m[4];
data_m = (data_m << 8) | pr->dmac_m[5];
break;
case TEMPLATE_FIELD_DMAC1:
data = pr->dmac[2];
data = (data << 8) | pr->dmac[3];
data_m = pr->dmac_m[2];
data_m = (data_m << 8) | pr->dmac_m[3];
break;
case TEMPLATE_FIELD_DMAC2:
data = pr->dmac[0];
data = (data << 8) | pr->dmac[1];
data_m = pr->dmac_m[0];
data_m = (data_m << 8) | pr->dmac_m[1];
break;
case TEMPLATE_FIELD_ETHERTYPE:
data = pr->ethertype;
data_m = pr->ethertype_m;
break;
case TEMPLATE_FIELD_ITAG:
data = pr->itag;
data_m = pr->itag_m;
break;
case TEMPLATE_FIELD_RANGE_CHK:
data = pr->field_range_check;
data_m = pr->field_range_check_m;
break;
case TEMPLATE_FIELD_SIP0:
if (pr->is_ipv6) {
data = pr->sip6.s6_addr16[7];
data_m = pr->sip6_m.s6_addr16[7];
} else {
data = pr->sip;
data_m = pr->sip_m;
}
break;
case TEMPLATE_FIELD_SIP1:
if (pr->is_ipv6) {
data = pr->sip6.s6_addr16[6];
data_m = pr->sip6_m.s6_addr16[6];
} else {
data = pr->sip >> 16;
data_m = pr->sip_m >> 16;
}
break;
case TEMPLATE_FIELD_SIP2:
case TEMPLATE_FIELD_SIP3:
case TEMPLATE_FIELD_SIP4:
case TEMPLATE_FIELD_SIP5:
case TEMPLATE_FIELD_SIP6:
case TEMPLATE_FIELD_SIP7:
data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
break;
case TEMPLATE_FIELD_DIP0:
if (pr->is_ipv6) {
data = pr->dip6.s6_addr16[7];
data_m = pr->dip6_m.s6_addr16[7];
} else {
data = pr->dip;
data_m = pr->dip_m;
}
break;
case TEMPLATE_FIELD_DIP1:
if (pr->is_ipv6) {
data = pr->dip6.s6_addr16[6];
data_m = pr->dip6_m.s6_addr16[6];
} else {
data = pr->dip >> 16;
data_m = pr->dip_m >> 16;
}
break;
case TEMPLATE_FIELD_DIP2:
case TEMPLATE_FIELD_DIP3:
case TEMPLATE_FIELD_DIP4:
case TEMPLATE_FIELD_DIP5:
case TEMPLATE_FIELD_DIP6:
case TEMPLATE_FIELD_DIP7:
data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
break;
case TEMPLATE_FIELD_IP_TOS_PROTO:
data = pr->tos_proto;
data_m = pr->tos_proto_m;
break;
case TEMPLATE_FIELD_L4_SPORT:
data = pr->sport;
data_m = pr->sport_m;
break;
case TEMPLATE_FIELD_L4_DPORT:
data = pr->dport;
data_m = pr->dport_m;
break;
case TEMPLATE_FIELD_ICMP_IGMP:
data = pr->icmp_igmp;
data_m = pr->icmp_igmp_m;
break;
default:
pr_info("%s: unknown field %d\n", __func__, field_type);
continue;
}
if (!(i % 2)) {
r[5 - i / 2] = data;
r[12 - i / 2] = data_m;
} else {
r[5 - i / 2] |= ((u32)data) << 16;
r[12 - i / 2] |= ((u32)data_m) << 16;
}
}
}
/*
* Creates the intermediate representation of the templated match-fields of the
* PIE rule in the pie_rule structure by reading the raw data fields in the
* raw register space r[].
* The register space configuration size is identical for the RTL8380/90 and RTL9300,
* however the RTL9310 has 2 more registers / fields and the physical field-ids
*/
static void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
{
int i;
enum template_field_id field_type;
u16 data, data_m;
for (i = 0; i < N_FIXED_FIELDS; i++) {
field_type = t[i];
if (!(i % 2)) {
data = r[5 - i / 2];
data_m = r[12 - i / 2];
} else {
data = r[5 - i / 2] >> 16;
data_m = r[12 - i / 2] >> 16;
}
switch (field_type) {
case TEMPLATE_FIELD_SPM0:
pr->spm = (pr->spn << 16) | data;
pr->spm_m = (pr->spn << 16) | data_m;
break;
case TEMPLATE_FIELD_SPM1:
pr->spm = data;
pr->spm_m = data_m;
break;
case TEMPLATE_FIELD_OTAG:
pr->otag = data;
pr->otag_m = data_m;
break;
case TEMPLATE_FIELD_SMAC0:
pr->smac[4] = data >> 8;
pr->smac[5] = data;
pr->smac_m[4] = data >> 8;
pr->smac_m[5] = data;
break;
case TEMPLATE_FIELD_SMAC1:
pr->smac[2] = data >> 8;
pr->smac[3] = data;
pr->smac_m[2] = data >> 8;
pr->smac_m[3] = data;
break;
case TEMPLATE_FIELD_SMAC2:
pr->smac[0] = data >> 8;
pr->smac[1] = data;
pr->smac_m[0] = data >> 8;
pr->smac_m[1] = data;
break;
case TEMPLATE_FIELD_DMAC0:
pr->dmac[4] = data >> 8;
pr->dmac[5] = data;
pr->dmac_m[4] = data >> 8;
pr->dmac_m[5] = data;
break;
case TEMPLATE_FIELD_DMAC1:
pr->dmac[2] = data >> 8;
pr->dmac[3] = data;
pr->dmac_m[2] = data >> 8;
pr->dmac_m[3] = data;
break;
case TEMPLATE_FIELD_DMAC2:
pr->dmac[0] = data >> 8;
pr->dmac[1] = data;
pr->dmac_m[0] = data >> 8;
pr->dmac_m[1] = data;
break;
case TEMPLATE_FIELD_ETHERTYPE:
pr->ethertype = data;
pr->ethertype_m = data_m;
break;
case TEMPLATE_FIELD_ITAG:
pr->itag = data;
pr->itag_m = data_m;
break;
case TEMPLATE_FIELD_RANGE_CHK:
pr->field_range_check = data;
pr->field_range_check_m = data_m;
break;
case TEMPLATE_FIELD_SIP0:
pr->sip = data;
pr->sip_m = data_m;
break;
case TEMPLATE_FIELD_SIP1:
pr->sip = (pr->sip << 16) | data;
pr->sip_m = (pr->sip << 16) | data_m;
break;
case TEMPLATE_FIELD_SIP2:
pr->is_ipv6 = true;
// Make use of limitiations on the position of the match values
ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
r[4 - i / 2], r[3 - i / 2]);
ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
r[4 - i / 2], r[3 - i / 2]);
case TEMPLATE_FIELD_SIP3:
case TEMPLATE_FIELD_SIP4:
case TEMPLATE_FIELD_SIP5:
case TEMPLATE_FIELD_SIP6:
case TEMPLATE_FIELD_SIP7:
break;
case TEMPLATE_FIELD_DIP0:
pr->dip = data;