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lantiq: fritz736x: Move GPIO resets to the inidvidual board.dts files
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FRITZ!Box 7360 V2 and FRITZ!Box 7360 SL both use GPIOs 37 (for &phy0)
and GPIO 44 (for &phy1) to control the PHY's reset lines. FRITZ!Box 7362
SL however uses GPIO 45 (for &phy0) and GPIO 44 (for &phy1). Move the
GPIO reset definitions to each individual board .dts and while at it,
fix the GPIOs for the FRITZ!Box 7362 SL.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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xdarklight authored and hauke committed Apr 16, 2022
1 parent e02fb42 commit 56cd49b
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Showing 4 changed files with 77 additions and 32 deletions.
Expand Up @@ -7,11 +7,23 @@
model = "AVM FRITZ!Box 7360 V2";
};

&state_default {
pcie-rst {
lantiq,pins = "io21";
lantiq,pull = <0>;
lantiq,output = <1>;
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;

state_default: pinmux {
pcie-rst {
lantiq,pins = "io21";
lantiq,pull = <0>;
lantiq,output = <1>;
};

phy-rst {
lantiq,pins = "io37", "io44";
lantiq,pull = <0>;
lantiq,open-drain;
lantiq,output = <1>;
};
};
};

Expand Down Expand Up @@ -58,6 +70,14 @@
mac-address-increment = <(-2)>;
};

&phy0 {
reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
};

&phy1 {
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};

&urlader {
compatible = "nvmem-cells";
#address-cells = <1>;
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Expand Up @@ -7,12 +7,25 @@
model = "AVM FRITZ!Box 7360 SL";
};

&state_default {
pcie-rst {
lantiq,pins = "io38";
lantiq,pull = <0>;
lantiq,output = <1>;
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;

state_default: pinmux {
pcie-rst {
lantiq,pins = "io21";
lantiq,pull = <0>;
lantiq,output = <1>;
};

phy-rst {
lantiq,pins = "io37", "io44";
lantiq,pull = <0>;
lantiq,open-drain;
lantiq,output = <1>;
};
};

};

&localbus {
Expand Down Expand Up @@ -58,6 +71,14 @@
mac-address-increment = <(-2)>;
};

&phy0 {
reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
};

&phy1 {
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};

&urlader {
compatible = "nvmem-cells";
#address-cells = <1>;
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Expand Up @@ -7,12 +7,25 @@
model = "AVM FRITZ!Box 7362 SL";
};

&state_default {
pcie-rst {
lantiq,pins = "io21";
lantiq,open-drain = <1>;
lantiq,output = <1>;
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;

state_default: pinmux {
pcie-rst {
lantiq,pins = "io21";
lantiq,pull = <0>;
lantiq,output = <1>;
};

phy-rst {
lantiq,pins = "io44", "io45";
lantiq,pull = <0>;
lantiq,open-drain;
lantiq,output = <1>;
};
};

};

&spi {
Expand Down Expand Up @@ -96,6 +109,14 @@
mac-address-increment = <(-2)>;
};

&phy0 {
reset-gpios = <&gpio 45 GPIO_ACTIVE_LOW>;
};

&phy1 {
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};

&urlader {
compatible = "nvmem-cells";
#address-cells = <1>;
Expand Down
Expand Up @@ -88,21 +88,6 @@
lantiq,gphy-mode = <GPHY_MODE_GE>;
};

&gpio {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;

state_default: pinmux {
phy-rst {
lantiq,pins = "io37", "io44";
lantiq,pull = <0>;
lantiq,open-drain;
lantiq,output = <1>;
};
};

};

&gswip {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
Expand All @@ -111,12 +96,10 @@
&gswip_mdio {
phy0: ethernet-phy@0 {
reg = <0x00>;
reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
};

phy1: ethernet-phy@1 {
reg = <0x01>;
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};

phy11: ethernet-phy@11 {
Expand Down

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