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mvebu: add support for iEi Puzzle-M901/Puzzle-M902
Hardware specification ---------------------- * CN9130 SoC, Quad-core ARMv8 Cortex-72 @ 2200 MHz * 4 GB DDR * 4 GB eMMC * mmcblk0 - mmcblk0p1 64M kernel_1 - mmcblk0p2 64M kernel_2 - mmcblk0p3 512M rootfs_1 - mmcblk0p4 512M rootfs_2 - mmcblk0p5 512M Reserved - mmcblk0p6 64M Reserved - mmcblk0p7 1.8G rootfs_data * 4 MB (SPI Flash) * 6 x 2.5 Gigabit ports (Puzzle-M901) - External PHY with 6 ports (AQR112R) * 6 x 2.5 Gigabit ports (Puzzle-M902) - External PHY with 6 ports (AQR112R) 3 x 10 Gigabit ports (Puzzle-M902) - External PHY with 3 ports (AQR113R) * 4 x Front panel LED * 1 x USB 3.0 * Reset button on Rear panel * UART (115200 8N1,header on PCB) Flash instructions: The original firmware is based on OpenWrt. Flash firmware using LuCI and CLI Signed-off-by: Ian Chang <ianchang@ieiworld.com>
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target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc-puzzle.sh
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platform_do_upgrade_emmc() { | ||
local board=$(board_name) | ||
local diskdev partdev | ||
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export_bootdevice && export_partdevice diskdev 0 || { | ||
v "Unable to determine upgrade device" | ||
return 1 | ||
} | ||
sync | ||
if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then | ||
get_partitions "/dev/$diskdev" bootdisk | ||
v "Extract boot sector from the image" | ||
get_image_dd "$1" of=/tmp/image.bs count=1 bs=512b | ||
get_partitions /tmp/image.bs image | ||
fi | ||
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#iterate over each partition from the image and write it to the boot disk | ||
while read part start size; do | ||
if export_partdevice partdev $part; then | ||
if [ "$partdev" = "mmcblk0p2" ]; then | ||
v "Writing image mmcblk0p3 for /dev/$partdev $start $size" | ||
get_image_dd "$1" of="/dev/mmcblk0p3" ibs="512" obs=1M skip="$start" count="$size" conv=fsync | ||
elif [ "$partdev" = "mmcblk0p1" ]; then | ||
v "Writing image mmcblk0p1 for /dev/$partdev $start $size" | ||
get_image_dd "$1" of="/dev/$partdev" ibs="512" obs=1M skip="$start" count="$size" conv=fsync | ||
fi | ||
else | ||
v "Unable to find partition $part device, skipped." | ||
fi | ||
done < /tmp/partmap.image | ||
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v "Writing new UUID to /dev/$diskdev..." | ||
get_image_dd "$1" of="/dev/$diskdev" bs=1 skip=440 count=4 seek=440 conv=fsync | ||
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sleep 1 | ||
} |
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target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) | ||
/* | ||
* Copyright (C) 2019 Marvell International Ltd. | ||
* | ||
* Device tree for the CN9131-DB board. | ||
*/ | ||
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#include "cn9130.dtsi" | ||
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#include <dt-bindings/gpio/gpio.h> | ||
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/ { | ||
model = "iEi Puzzle-M901"; | ||
compatible = "iei,puzzle-m901", | ||
"marvell,armada-ap807-quad", "marvell,armada-ap807"; | ||
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chosen { | ||
stdout-path = "serial0:115200n8"; | ||
}; | ||
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aliases { | ||
i2c0 = &cp1_i2c0; | ||
i2c1 = &cp0_i2c0; | ||
ethernet0 = &cp0_eth0; | ||
ethernet1 = &cp0_eth1; | ||
ethernet2 = &cp0_eth2; | ||
ethernet3 = &cp1_eth0; | ||
ethernet4 = &cp1_eth1; | ||
ethernet5 = &cp1_eth2; | ||
gpio1 = &cp0_gpio1; | ||
gpio2 = &cp0_gpio2; | ||
gpio3 = &cp1_gpio1; | ||
gpio4 = &cp1_gpio2; | ||
}; | ||
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memory@00000000 { | ||
device_type = "memory"; | ||
reg = <0x0 0x0 0x0 0x80000000>; | ||
}; | ||
}; | ||
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&uart0 { | ||
status = "okay"; | ||
}; | ||
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&cp0_uart0 { | ||
status = "okay"; | ||
}; | ||
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/* on-board eMMC - U9 */ | ||
&ap_sdhci0 { | ||
pinctrl-names = "default"; | ||
bus-width = <8>; | ||
status = "okay"; | ||
mmc-ddr-1_8v; | ||
mmc-hs400-1_8v; | ||
}; | ||
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&cp0_crypto { | ||
status = "okay"; | ||
}; | ||
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&cp0_xmdio { | ||
status = "okay"; | ||
cp0_nbaset_phy0: ethernet-phy@0 { | ||
compatible = "ethernet-phy-ieee802.3-c45"; | ||
reg = <2>; | ||
}; | ||
cp0_nbaset_phy1: ethernet-phy@1 { | ||
compatible = "ethernet-phy-ieee802.3-c45"; | ||
reg = <0>; | ||
}; | ||
cp0_nbaset_phy2: ethernet-phy@2 { | ||
compatible = "ethernet-phy-ieee802.3-c45"; | ||
reg = <8>; | ||
}; | ||
}; | ||
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&cp0_ethernet { | ||
status = "okay"; | ||
}; | ||
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/* SLM-1521-V2, CON9 */ | ||
&cp0_eth0 { | ||
status = "okay"; | ||
phy-mode = "2500base-x"; | ||
phys = <&cp0_comphy2 0>; | ||
managed = "in-band-status"; | ||
}; | ||
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&cp0_eth1 { | ||
status = "okay"; | ||
phy-mode = "2500base-x"; | ||
phys = <&cp0_comphy4 1>; | ||
managed = "in-band-status"; | ||
}; | ||
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&cp0_eth2 { | ||
status = "okay"; | ||
phy-mode = "2500base-x"; | ||
phys = <&cp0_comphy5 2>; | ||
managed = "in-band-status"; | ||
}; | ||
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&cp0_gpio1 { | ||
status = "okay"; | ||
}; | ||
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&cp0_gpio2 { | ||
status = "okay"; | ||
}; | ||
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&cp0_i2c0 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&cp0_i2c0_pins>; | ||
status = "okay"; | ||
clock-frequency = <100000>; | ||
rtc@32 { | ||
compatible = "epson,rx8130"; | ||
reg = <0x32>; | ||
wakeup-source; | ||
}; | ||
}; | ||
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/* SLM-1521-V2, CON6 */ | ||
&cp0_pcie0 { | ||
status = "okay"; | ||
num-lanes = <2>; | ||
num-viewport = <8>; | ||
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>; | ||
}; | ||
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/* U55 */ | ||
&cp0_spi1 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&cp0_spi0_pins>; | ||
reg = <0x700680 0x50>, /* control */ | ||
<0x2000000 0x1000000>; /* CS0 */ | ||
status = "okay"; | ||
spi-flash@0 { | ||
#address-cells = <0x1>; | ||
#size-cells = <0x1>; | ||
compatible = "jedec,spi-nor"; | ||
reg = <0x0>; | ||
spi-max-frequency = <40000000>; | ||
partitions { | ||
compatible = "fixed-partitions"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
partition@0 { | ||
label = "U-Boot"; | ||
reg = <0x0 0x1f0000>; | ||
}; | ||
partition@1f0000 { | ||
label = "U-Boot ENV Factory"; | ||
reg = <0x1f0000 0x10000>; | ||
}; | ||
partition@200000 { | ||
label = "Reserved"; | ||
reg = <0x200000 0x1f0000>; | ||
}; | ||
partition@3f0000 { | ||
label = "U-Boot ENV"; | ||
reg = <0x3f0000 0x10000>; | ||
}; | ||
}; | ||
}; | ||
}; | ||
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&cp0_syscon0 { | ||
cp0_pinctrl: pinctrl { | ||
compatible = "marvell,cp115-standalone-pinctrl"; | ||
cp0_i2c0_pins: cp0-i2c-pins-0 { | ||
marvell,pins = "mpp37", "mpp38"; | ||
marvell,function = "i2c0"; | ||
}; | ||
cp0_i2c1_pins: cp0-i2c-pins-1 { | ||
marvell,pins = "mpp35", "mpp36"; | ||
marvell,function = "i2c1"; | ||
}; | ||
cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { | ||
marvell,pins = "mpp0", "mpp1", "mpp2", | ||
"mpp3", "mpp4", "mpp5", | ||
"mpp6", "mpp7", "mpp8", | ||
"mpp9", "mpp10", "mpp11"; | ||
marvell,function = "ge0"; | ||
}; | ||
cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { | ||
marvell,pins = "mpp44", "mpp45", "mpp46", | ||
"mpp47", "mpp48", "mpp49", | ||
"mpp50", "mpp51", "mpp52", | ||
"mpp53", "mpp54", "mpp55"; | ||
marvell,function = "ge1"; | ||
}; | ||
cp0_spi0_pins: cp0-spi-pins-0 { | ||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; | ||
marvell,function = "spi1"; | ||
}; | ||
}; | ||
}; | ||
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/* | ||
* Instantiate the first connected CP115 | ||
*/ | ||
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#define CP11X_NAME cp1 | ||
#define CP11X_BASE f6000000 | ||
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) | ||
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 | ||
#define CP11X_PCIE0_BASE f6600000 | ||
#define CP11X_PCIE1_BASE f6620000 | ||
#define CP11X_PCIE2_BASE f6640000 | ||
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#include "armada-cp115.dtsi" | ||
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#undef CP11X_NAME | ||
#undef CP11X_BASE | ||
#undef CP11X_PCIEx_MEM_BASE | ||
#undef CP11X_PCIEx_MEM_SIZE | ||
#undef CP11X_PCIE0_BASE | ||
#undef CP11X_PCIE1_BASE | ||
#undef CP11X_PCIE2_BASE | ||
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&cp1_crypto { | ||
status = "okay"; | ||
}; | ||
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&cp1_xmdio { | ||
status = "okay"; | ||
cp1_nbaset_phy0: ethernet-phy@3 { | ||
compatible = "ethernet-phy-ieee802.3-c45"; | ||
reg = <2>; | ||
}; | ||
cp1_nbaset_phy1: ethernet-phy@4 { | ||
compatible = "ethernet-phy-ieee802.3-c45"; | ||
reg = <0>; | ||
}; | ||
cp1_nbaset_phy2: ethernet-phy@5 { | ||
compatible = "ethernet-phy-ieee802.3-c45"; | ||
reg = <8>; | ||
}; | ||
}; | ||
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&cp1_ethernet { | ||
status = "okay"; | ||
}; | ||
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/* CON50 */ | ||
&cp1_eth0 { | ||
status = "okay"; | ||
phy-mode = "2500base-x"; | ||
phys = <&cp1_comphy2 0>; | ||
managed = "in-band-status"; | ||
}; | ||
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&cp1_eth1 { | ||
status = "okay"; | ||
phy-mode = "2500base-x"; | ||
phys = <&cp1_comphy4 1>; | ||
managed = "in-band-status"; | ||
}; | ||
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&cp1_eth2 { | ||
status = "okay"; | ||
phy-mode = "2500base-x"; | ||
phys = <&cp1_comphy5 2>; | ||
managed = "in-band-status"; | ||
}; | ||
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&cp1_sata0 { | ||
status = "okay"; | ||
sata-port@1 { | ||
status = "okay"; | ||
phys = <&cp1_comphy0 1>; | ||
}; | ||
}; | ||
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&cp1_gpio1 { | ||
status = "okay"; | ||
}; | ||
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&cp1_gpio2 { | ||
status = "okay"; | ||
}; | ||
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&cp1_i2c0 { | ||
status = "okay"; | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&cp1_i2c0_pins>; | ||
clock-frequency = <100000>; | ||
}; | ||
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&cp1_syscon0 { | ||
cp1_pinctrl: pinctrl { | ||
compatible = "marvell,cp115-standalone-pinctrl"; | ||
cp1_i2c0_pins: cp1-i2c-pins-0 { | ||
marvell,pins = "mpp37", "mpp38"; | ||
marvell,function = "i2c0"; | ||
}; | ||
cp1_spi0_pins: cp1-spi-pins-0 { | ||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; | ||
marvell,function = "spi1"; | ||
}; | ||
cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { | ||
marvell,pins = "mpp3"; | ||
marvell,function = "gpio"; | ||
}; | ||
cp1_sfp_pins: sfp-pins { | ||
marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11"; | ||
marvell,function = "gpio"; | ||
}; | ||
}; | ||
}; | ||
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&cp1_usb3_1 { | ||
status = "okay"; | ||
phys = <&cp1_comphy3 1>; | ||
phy-names = "usb"; | ||
}; |
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