forked from openwrt/openwrt
-
-
Notifications
You must be signed in to change notification settings - Fork 5
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
bcm4908: backport bcmbca DT patches queued for 5.20
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
- Loading branch information
Rafał Miłecki
committed
Jul 20, 2022
1 parent
d1b5d17
commit d63ef7c
Showing
10 changed files
with
1,161 additions
and
0 deletions.
There are no files selected for viewing
199 changes: 199 additions & 0 deletions
199
...bcm4908/patches-5.10/037-v5.20-0001-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63158.patch
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,199 @@ | ||
From 076dcedc6628c6bf92bd17bfcf8fb7b1af62bfb6 Mon Sep 17 00:00:00 2001 | ||
From: William Zhang <william.zhang@broadcom.com> | ||
Date: Wed, 1 Jun 2022 15:56:51 -0700 | ||
Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63158 | ||
|
||
Add DTS for ARMv8 based broadband SoC BCM63158. bcm63158.dtsi is the | ||
SoC description DTS header and bcm963158.dts is a simple DTS file for | ||
Broadcom BCM963158 Reference board that only enable the UART port. | ||
|
||
Signed-off-by: William Zhang <william.zhang@broadcom.com> | ||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> | ||
--- | ||
arch/arm64/boot/dts/broadcom/Makefile | 1 + | ||
arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 2 + | ||
.../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 128 ++++++++++++++++++ | ||
.../boot/dts/broadcom/bcmbca/bcm963158.dts | 30 ++++ | ||
4 files changed, 161 insertions(+) | ||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/Makefile | ||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | ||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts | ||
|
||
--- a/arch/arm64/boot/dts/broadcom/Makefile | ||
+++ b/arch/arm64/boot/dts/broadcom/Makefile | ||
@@ -6,5 +6,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rp | ||
bcm2837-rpi-cm3-io3.dtb | ||
|
||
subdir-y += bcm4908 | ||
+subdir-y += bcmbca | ||
subdir-y += northstar2 | ||
subdir-y += stingray | ||
--- /dev/null | ||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile | ||
@@ -0,0 +1,2 @@ | ||
+# SPDX-License-Identifier: GPL-2.0 | ||
+dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb | ||
--- /dev/null | ||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | ||
@@ -0,0 +1,128 @@ | ||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||
+/* | ||
+ * Copyright 2022 Broadcom Ltd. | ||
+ */ | ||
+ | ||
+#include <dt-bindings/interrupt-controller/irq.h> | ||
+#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
+ | ||
+/ { | ||
+ compatible = "brcm,bcm63158", "brcm,bcmbca"; | ||
+ #address-cells = <2>; | ||
+ #size-cells = <2>; | ||
+ | ||
+ interrupt-parent = <&gic>; | ||
+ | ||
+ cpus { | ||
+ #address-cells = <2>; | ||
+ #size-cells = <0>; | ||
+ | ||
+ B53_0: cpu@0 { | ||
+ compatible = "brcm,brahma-b53"; | ||
+ device_type = "cpu"; | ||
+ reg = <0x0 0x0>; | ||
+ next-level-cache = <&L2_0>; | ||
+ enable-method = "psci"; | ||
+ }; | ||
+ | ||
+ B53_1: cpu@1 { | ||
+ compatible = "brcm,brahma-b53"; | ||
+ device_type = "cpu"; | ||
+ reg = <0x0 0x1>; | ||
+ next-level-cache = <&L2_0>; | ||
+ enable-method = "psci"; | ||
+ }; | ||
+ | ||
+ B53_2: cpu@2 { | ||
+ compatible = "brcm,brahma-b53"; | ||
+ device_type = "cpu"; | ||
+ reg = <0x0 0x2>; | ||
+ next-level-cache = <&L2_0>; | ||
+ enable-method = "psci"; | ||
+ }; | ||
+ | ||
+ B53_3: cpu@3 { | ||
+ compatible = "brcm,brahma-b53"; | ||
+ device_type = "cpu"; | ||
+ reg = <0x0 0x3>; | ||
+ next-level-cache = <&L2_0>; | ||
+ enable-method = "psci"; | ||
+ }; | ||
+ | ||
+ L2_0: l2-cache0 { | ||
+ compatible = "cache"; | ||
+ }; | ||
+ }; | ||
+ | ||
+ timer { | ||
+ compatible = "arm,armv8-timer"; | ||
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | ||
+ }; | ||
+ | ||
+ pmu: pmu { | ||
+ compatible = "arm,cortex-a53-pmu"; | ||
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | ||
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | ||
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | ||
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | ||
+ interrupt-affinity = <&B53_0>, <&B53_1>, | ||
+ <&B53_2>, <&B53_3>; | ||
+ }; | ||
+ | ||
+ clocks: clocks { | ||
+ periph_clk: periph-clk { | ||
+ compatible = "fixed-clock"; | ||
+ #clock-cells = <0>; | ||
+ clock-frequency = <200000000>; | ||
+ }; | ||
+ uart_clk: uart-clk { | ||
+ compatible = "fixed-factor-clock"; | ||
+ #clock-cells = <0>; | ||
+ clocks = <&periph_clk>; | ||
+ clock-div = <4>; | ||
+ clock-mult = <1>; | ||
+ }; | ||
+ }; | ||
+ | ||
+ psci { | ||
+ compatible = "arm,psci-0.2"; | ||
+ method = "smc"; | ||
+ }; | ||
+ | ||
+ axi@81000000 { | ||
+ compatible = "simple-bus"; | ||
+ #address-cells = <1>; | ||
+ #size-cells = <1>; | ||
+ ranges = <0x0 0x0 0x81000000 0x8000>; | ||
+ | ||
+ gic: interrupt-controller@1000 { | ||
+ compatible = "arm,gic-400"; | ||
+ #interrupt-cells = <3>; | ||
+ interrupt-controller; | ||
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | ||
+ reg = <0x1000 0x1000>, | ||
+ <0x2000 0x2000>, | ||
+ <0x4000 0x2000>, | ||
+ <0x6000 0x2000>; | ||
+ }; | ||
+ }; | ||
+ | ||
+ bus@ff800000 { | ||
+ compatible = "simple-bus"; | ||
+ #address-cells = <1>; | ||
+ #size-cells = <1>; | ||
+ ranges = <0x0 0x0 0xff800000 0x800000>; | ||
+ | ||
+ uart0: serial@12000 { | ||
+ compatible = "arm,pl011", "arm,primecell"; | ||
+ reg = <0x12000 0x1000>; | ||
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | ||
+ clocks = <&uart_clk>, <&uart_clk>; | ||
+ clock-names = "uartclk", "apb_pclk"; | ||
+ status = "disabled"; | ||
+ }; | ||
+ }; | ||
+}; | ||
--- /dev/null | ||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts | ||
@@ -0,0 +1,30 @@ | ||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||
+/* | ||
+ * Copyright 2022 Broadcom Ltd. | ||
+ */ | ||
+ | ||
+/dts-v1/; | ||
+ | ||
+#include "bcm63158.dtsi" | ||
+ | ||
+/ { | ||
+ model = "Broadcom BCM963158 Reference Board"; | ||
+ compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca"; | ||
+ | ||
+ aliases { | ||
+ serial0 = &uart0; | ||
+ }; | ||
+ | ||
+ chosen { | ||
+ stdout-path = "serial0:115200n8"; | ||
+ }; | ||
+ | ||
+ memory@0 { | ||
+ device_type = "memory"; | ||
+ reg = <0x0 0x0 0x0 0x08000000>; | ||
+ }; | ||
+}; | ||
+ | ||
+&uart0 { | ||
+ status = "okay"; | ||
+}; |
191 changes: 191 additions & 0 deletions
191
.../bcm4908/patches-5.10/037-v5.20-0002-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM4912.patch
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,191 @@ | ||
From 1ba56aeb391401c4cb2126c39f90b3cdbfabdb3f Mon Sep 17 00:00:00 2001 | ||
From: William Zhang <william.zhang@broadcom.com> | ||
Date: Wed, 1 Jun 2022 13:17:34 -0700 | ||
Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM4912 | ||
|
||
Add DTS for ARMv8 based broadband SoC BCM4912. bcm4912.dtsi is the | ||
SoC description DTS header and bcm94912.dts is a simple DTS file for | ||
Broadcom BCM94912 Reference board that only enable the UART port. | ||
|
||
Signed-off-by: William Zhang <william.zhang@broadcom.com> | ||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | ||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> | ||
--- | ||
arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- | ||
.../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 128 ++++++++++++++++++ | ||
.../boot/dts/broadcom/bcmbca/bcm94912.dts | 30 ++++ | ||
3 files changed, 160 insertions(+), 1 deletion(-) | ||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | ||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts | ||
|
||
--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile | ||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile | ||
@@ -1,2 +1,3 @@ | ||
# SPDX-License-Identifier: GPL-2.0 | ||
-dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb | ||
+dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \ | ||
+ bcm963158.dtb | ||
--- /dev/null | ||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | ||
@@ -0,0 +1,128 @@ | ||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||
+/* | ||
+ * Copyright 2022 Broadcom Ltd. | ||
+ */ | ||
+ | ||
+#include <dt-bindings/interrupt-controller/irq.h> | ||
+#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
+ | ||
+/ { | ||
+ compatible = "brcm,bcm4912", "brcm,bcmbca"; | ||
+ #address-cells = <2>; | ||
+ #size-cells = <2>; | ||
+ | ||
+ interrupt-parent = <&gic>; | ||
+ | ||
+ cpus { | ||
+ #address-cells = <2>; | ||
+ #size-cells = <0>; | ||
+ | ||
+ B53_0: cpu@0 { | ||
+ compatible = "brcm,brahma-b53"; | ||
+ device_type = "cpu"; | ||
+ reg = <0x0 0x0>; | ||
+ next-level-cache = <&L2_0>; | ||
+ enable-method = "psci"; | ||
+ }; | ||
+ | ||
+ B53_1: cpu@1 { | ||
+ compatible = "brcm,brahma-b53"; | ||
+ device_type = "cpu"; | ||
+ reg = <0x0 0x1>; | ||
+ next-level-cache = <&L2_0>; | ||
+ enable-method = "psci"; | ||
+ }; | ||
+ | ||
+ B53_2: cpu@2 { | ||
+ compatible = "brcm,brahma-b53"; | ||
+ device_type = "cpu"; | ||
+ reg = <0x0 0x2>; | ||
+ next-level-cache = <&L2_0>; | ||
+ enable-method = "psci"; | ||
+ }; | ||
+ | ||
+ B53_3: cpu@3 { | ||
+ compatible = "brcm,brahma-b53"; | ||
+ device_type = "cpu"; | ||
+ reg = <0x0 0x3>; | ||
+ next-level-cache = <&L2_0>; | ||
+ enable-method = "psci"; | ||
+ }; | ||
+ | ||
+ L2_0: l2-cache0 { | ||
+ compatible = "cache"; | ||
+ }; | ||
+ }; | ||
+ | ||
+ timer { | ||
+ compatible = "arm,armv8-timer"; | ||
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | ||
+ }; | ||
+ | ||
+ pmu: pmu { | ||
+ compatible = "arm,cortex-a53-pmu"; | ||
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | ||
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | ||
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | ||
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | ||
+ interrupt-affinity = <&B53_0>, <&B53_1>, | ||
+ <&B53_2>, <&B53_3>; | ||
+ }; | ||
+ | ||
+ clocks: clocks { | ||
+ periph_clk: periph-clk { | ||
+ compatible = "fixed-clock"; | ||
+ #clock-cells = <0>; | ||
+ clock-frequency = <200000000>; | ||
+ }; | ||
+ uart_clk: uart-clk { | ||
+ compatible = "fixed-factor-clock"; | ||
+ #clock-cells = <0>; | ||
+ clocks = <&periph_clk>; | ||
+ clock-div = <4>; | ||
+ clock-mult = <1>; | ||
+ }; | ||
+ }; | ||
+ | ||
+ psci { | ||
+ compatible = "arm,psci-0.2"; | ||
+ method = "smc"; | ||
+ }; | ||
+ | ||
+ axi@81000000 { | ||
+ compatible = "simple-bus"; | ||
+ #address-cells = <1>; | ||
+ #size-cells = <1>; | ||
+ ranges = <0x0 0x0 0x81000000 0x8000>; | ||
+ | ||
+ gic: interrupt-controller@1000 { | ||
+ compatible = "arm,gic-400"; | ||
+ #interrupt-cells = <3>; | ||
+ interrupt-controller; | ||
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | ||
+ reg = <0x1000 0x1000>, | ||
+ <0x2000 0x2000>, | ||
+ <0x4000 0x2000>, | ||
+ <0x6000 0x2000>; | ||
+ }; | ||
+ }; | ||
+ | ||
+ bus@ff800000 { | ||
+ compatible = "simple-bus"; | ||
+ #address-cells = <1>; | ||
+ #size-cells = <1>; | ||
+ ranges = <0x0 0x0 0xff800000 0x800000>; | ||
+ | ||
+ uart0: serial@12000 { | ||
+ compatible = "arm,pl011", "arm,primecell"; | ||
+ reg = <0x12000 0x1000>; | ||
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | ||
+ clocks = <&uart_clk>, <&uart_clk>; | ||
+ clock-names = "uartclk", "apb_pclk"; | ||
+ status = "disabled"; | ||
+ }; | ||
+ }; | ||
+}; | ||
--- /dev/null | ||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts | ||
@@ -0,0 +1,30 @@ | ||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||
+/* | ||
+ * Copyright 2022 Broadcom Ltd. | ||
+ */ | ||
+ | ||
+/dts-v1/; | ||
+ | ||
+#include "bcm4912.dtsi" | ||
+ | ||
+/ { | ||
+ model = "Broadcom BCM94912 Reference Board"; | ||
+ compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca"; | ||
+ | ||
+ aliases { | ||
+ serial0 = &uart0; | ||
+ }; | ||
+ | ||
+ chosen { | ||
+ stdout-path = "serial0:115200n8"; | ||
+ }; | ||
+ | ||
+ memory@0 { | ||
+ device_type = "memory"; | ||
+ reg = <0x0 0x0 0x0 0x08000000>; | ||
+ }; | ||
+}; | ||
+ | ||
+&uart0 { | ||
+ status = "okay"; | ||
+}; |
Oops, something went wrong.