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Update SDRAM cart to Rev B.

Signed-off-by: Michael Welling <mwelling@ieee.org>
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mwelling committed Dec 20, 2019
1 parent 92674d2 commit ea6eb418675d66745026614959671ff026f1212a
Showing with 22 additions and 22 deletions.
  1. +22 −22 litex_boards/partner/platforms/hadbadge.py
@@ -96,34 +96,34 @@
Subsignal("b3", Pins("A13")),
Subsignal("b4", Pins("B13")),
),
# ("sdram_clock", 0, Pins("22"), IOStandard("LVCMOS33")),
# rev a
# ("sdram_clock", 0, Pins("C11"), IOStandard("LVCMOS33")),
# ("sdram", 0,
# Subsignal("a", Pins("17 18 19 20 30 29 28 27 26 25 16 24 09")),
# Subsignal("dq", Pins("01 03 05 07 02 04 06 08")),
# Subsignal("we_n", Pins("10")),
# Subsignal("ras_n", Pins("12")),
# Subsignal("cas_n", Pins("11")),
# Subsignal("cs_n", Pins("13")),
# Subsignal("cke", Pins("23")),
# Subsignal("ba", Pins("14 15")),
# Subsignal("dm", Pins("21")),
# Subsignal("a", Pins("D10 C10 B10 A10 C14 E17 A12 B12 H17 G18 A9 A11 A7")),
# Subsignal("dq", Pins("C5 A5 B6 D6 B5 C6 A6 C7")),
# Subsignal("we_n", Pins("C8")),
# Subsignal("ras_n", Pins("A8")),
# Subsignal("cas_n", Pins("B8")),
# Subsignal("cs_n", Pins("D9")),
# Subsignal("cke", Pins("B11")),
# Subsignal("ba", Pins("C9 B9")),
# Subsignal("dm", Pins("D11")),
# IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
# ),
("sdram_clock", 0, Pins("C11"), IOStandard("LVCMOS33")),
# rev b
("sdram_clock", 0, Pins("D11"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins("D10 C10 B10 A10 C14 E17 A12 B12 H17 G18 A9 A11 A7")),
Subsignal("dq", Pins("C5 A5 B6 D6 B5 C6 A6 C7")),
Subsignal("we_n", Pins("C8")),
Subsignal("ras_n", Pins("A8")),
Subsignal("cas_n", Pins("B8")),
Subsignal("cs_n", Pins("D9")),
Subsignal("cke", Pins("B11")),
Subsignal("ba", Pins("C9 B9")),
Subsignal("dm", Pins("D11")),
Subsignal("a", Pins("A8 D9 C9 B9 C14 E17 A12 B12 H17 G18 B8 A11 B11")),
Subsignal("dq", Pins("C5 B5 A5 C6 B10 C10 D10 A9")),
Subsignal("we_n", Pins("B6")),
Subsignal("ras_n", Pins("D6")),
Subsignal("cas_n", Pins("A6")),
Subsignal("cs_n", Pins("C7")),
Subsignal("cke", Pins("C11")),
Subsignal("ba", Pins("A7 C8")),
Subsignal("dm", Pins("A10")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
),
#("C5 B5 A5 C6 B6 A6 D6 C7 A7 C8 B8 A8 D9 C9 B9 A9 D10 C10 B10 A10 D11 C11 B11 A11 G18 H17 B12 A12 E17 C14"),
#("01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 "),

# Only used for simulation
("wishbone", 0,

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