RISC-V: Add runtime invariant support

RISC-V 'V' Extension support scalable vector like ARM SVE.
To support RVV, we need to introduce runtime invariant.

- For zve32*, the runtime invariant uses 32-bit chunk.
- For zve64*, the runtime invariant uses 64-bit chunk.

[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#sec-vector-extensions

This patch is preparing patch for RVV support.
Because we didn't introduce vector machine_mode yet, it safe to just change HOST_WIDE_INT into poly_int.
Also it safe to use "to_constant()" function for scalar operation.
This patch has been tested by full dejagnu regression.

gcc/ChangeLog:

	* config/riscv/predicates.md: Adjust runtime invariant.
	* config/riscv/riscv-modes.def (MAX_BITSIZE_MODE_ANY_MODE): New.
	(NUM_POLY_INT_COEFFS): New.
	* config/riscv/riscv-protos.h (riscv_initial_elimination_offset):Adjust
	runtime invariant.
	* config/riscv/riscv-sr.cc (riscv_remove_unneeded_save_restore_calls):
	Adjust runtime invariant.
	* config/riscv/riscv.cc (struct riscv_frame_info): Adjust runtime
	invariant.
	(enum riscv_microarchitecture_type): Ditto.
	(riscv_valid_offset_p): Ditto.
	(riscv_valid_lo_sum_p): Ditto.
	(riscv_address_insns): Ditto.
	(riscv_load_store_insns): Ditto.
	(riscv_legitimize_move): Ditto.
	(riscv_binary_cost): Ditto.
	(riscv_rtx_costs): Ditto.
	(riscv_output_move): Ditto.
	(riscv_extend_comparands): Ditto.
	(riscv_flatten_aggregate_field): Ditto.
	(riscv_get_arg_info): Ditto.
	(riscv_pass_by_reference): Ditto.
	(riscv_elf_select_rtx_section): Ditto.
	(riscv_stack_align): Ditto.
	(riscv_compute_frame_info): Ditto.
	(riscv_initial_elimination_offset): Ditto.
	(riscv_set_return_address): Ditto.
	(riscv_for_each_saved_reg): Ditto.
	(riscv_first_stack_step): Ditto.
	(riscv_expand_prologue): Ditto.
	(riscv_expand_epilogue): Ditto.
	(riscv_can_use_return_insn): Ditto.
	(riscv_secondary_memory_needed): Ditto.
	(riscv_hard_regno_nregs): Ditto.
	(riscv_convert_vector_bits): New.
	(riscv_option_override): Adjust runtime invariant.
	(riscv_promote_function_mode): Ditto.
	* config/riscv/riscv.h (POLY_SMALL_OPERAND_P): New.
	(BITS_PER_RISCV_VECTOR): New.
	(BYTES_PER_RISCV_VECTOR): New.
	* config/riscv/riscv.md: Adjust runtime invariant.

gcc/config/riscv/predicates.md

@@ -71,7 +71,7 @@
 {
   /* Don't handle multi-word moves this way; we don't want to introduce
      the individual word-mode moves until after reload.  */
-  if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+  if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
     return false;
 
   /* Check whether the constant can be loaded in a single

gcc/config/riscv/riscv-modes.def

@@ -21,3 +21,16 @@ along with GCC; see the file COPYING3.  If not see
 
 FLOAT_MODE (HF, 2, ieee_half_format);
 FLOAT_MODE (TF, 16, ieee_quad_format);
+
+/* TODO: According to RISC-V 'V' ISA spec, the maximun vector length can
+   be 65536 for a single vector register which means the vector mode in
+   GCC can be maximum = 65536 * 8 bits (LMUL=8).
+   However, 'GET_MODE_SIZE' is using poly_uint16/unsigned short which will
+   overflow if we specify vector-length = 65536. To support this feature,
+   we need to change the codes outside the RISC-V port. We will support it in
+   the future.  */
+#define MAX_BITSIZE_MODE_ANY_MODE (4096 * 8)
+
+/* Coefficient 1 is multiplied by the number of 64-bit/32-bit chunks in a vector
+   minus one.  */
+#define NUM_POLY_INT_COEFFS 2

gcc/config/riscv/riscv-protos.h

@@ -64,7 +64,7 @@ extern rtx riscv_legitimize_call_address (rtx);
 extern void riscv_set_return_address (rtx, rtx);
 extern bool riscv_expand_block_move (rtx, rtx, rtx);
 extern rtx riscv_return_addr (int, rtx);
-extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int);
+extern poly_int64 riscv_initial_elimination_offset (int, int);
 extern void riscv_expand_prologue (void);
 extern void riscv_expand_epilogue (int);
 extern bool riscv_epilogue_uses (unsigned int);

gcc/config/riscv/riscv-sr.cc

@@ -247,7 +247,7 @@ riscv_remove_unneeded_save_restore_calls (void)
   /* We'll adjust stack size after this optimization, that require update every
      sp use site, which could be unsafe, so we decide to turn off this
      optimization if there are any arguments put on stack.  */
-  if (crtl->args.size != 0)
+  if (known_ne (crtl->args.size, 0))
     return;
 
   /* Will point to the first instruction of the function body, after the